PNX1500E/G,557 NXP Semiconductors, PNX1500E/G,557 Datasheet - Page 144

• Manufacturer Part Number: PNX1500E/G,557
• Description: IC MEDIA PROC 240MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E/G,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.14 V ~ 1.26 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 568-1296; 935277746557; PNX1500E/G

NXP Semiconductors
Volume 1 of 1
PNX15XX_PNX952X_SER_N_4
Product data sheet
2.2.1 The Non Interrupt Mode
2.2 The watchdog Timer
The internal PNX15xx/952x Series watchdog timer has two operating modes. Both
modes result in the assertion of the internal reset signals, peri_rst_n and
sys_rst_out_n signals based upon a time-out condition. The modes are referenced as
the non interrupt mode and the interrupt mode.
In this mode, the watchdog timer operates as a simple counter. The counter operates
with the DCS clock also called MMIO clock (clk_dtl_mmio).
By default, i.e. after a PNX15xx/952x Series system reset, this watchdog counter is
not active. The activation is done by writing a value different than 0x0 to the
WATCHDOG_COUNT MMIO register. Upon that write, an internal counter of the
watchdog timer is reset to 0x0 and starts to count. If the internal counter reaches the
WATCHDOG_COUNT value then peri_rst_n and sys_rst_out_n internal reset signals
are asserted and the PNX15xx/952x Series system is reset. The reset follows then
the regular software reset timing,
WATCHDOG_COUNT MMIO register before the internal counter reaches the
previous WATCHDOG_COUNT value then the internal reset signals are not
generated and the internal counter stops counting. Similarly if the CPU writes a value
different than 0x0 then the internal counter is reset to 0x0 and starts to count to the
new WATCHDOG_COUNT value.
This mode requires the CPU to come back in time to reset the internal counter on a
regular basis. TM3260 software may use some of its internal hardware timers [1] to
reset on time on the internal counter. The interrupt handler needs to first write a 0x0
value to the WATCHDOG_COUNT register then write a new count value.
The layout of the WATCHDOG_COUNT MMIO register is presented in
The following summarizes the sequence of operations
1. Start the internal counter by writing a nonzero value to the WATCHDOG_COUNT
2. A write with 0x0 value to the WATCHDOG_COUNT MMIO register will stop the
3. If step 2 does not occur before the count reaches the WATCHDOG_COUNT
MMIO register.
count. For continuous watchdog timer operation it is not required to write 0x0 first
but instead start back directly from step 1).
value the PNX15xx/952x Series system reset is asserted.
Rev. 4.0 — 03 December 2007
Section
3.2. If the CPU writes a 0x0 value to the
PNX15xx/952x Series
© NXP B.V. 2007. All rights reserved.
Chapter 4: Reset
Section
4..
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