MPC8343VRAGDB Freescale Semiconductor, MPC8343VRAGDB Datasheet - Page 12

• Manufacturer Part Number: MPC8343VRAGDB
• Description: IC MPU POWERQUICC II 620-PBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8343VRAGDB

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 620-PBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: MPC8349E-MITXE
• Maximum Clock Frequency: 400 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 400MHz
• Embedded Interface Type: I2C, SPI, USB, UART
• Digital Ic Case Style: BGA
• No. Of Pins: 620
• Rohs Compliant: Yes
• Family Name: MPC83xx
• Device Core: PowerQUICC II Pro
• Device Core Size: 32b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2V
• Operating Supply Voltage (max): 1.26V
• Operating Supply Voltage (min): 1.14V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 620
• Package Type: BGA
• For Use With: CWH-PPC-8343N-VX - KIT EVAL SYSTEM QUICCSTART 8248CWH-PPC-8343N-VE - EVALUATION SYSTEM QUICC MPC8343E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

RESET Initialization
4.3
Table 8
5
This section describes the DC and AC electrical specifications for the reset initialization timing and
electrical requirements of the MPC8343EA.
12
At recommended operating conditions with LV
EC_GTX_CLK125 frequency
EC_GTX_CLK125 cycle time
EC_GTX_CLK rise and fall time
EC_GTX_CLK125 duty cycle
EC_GTX_CLK125 jitter
Notes:
1. Rise and fall times for EC_GTX_CLK125 are measured from 0.5 and 2.0 V for LV
2. EC_GTX_CLK125 is used to generate the GTX clock for the eTSEC transmitter with 2% degradation. The EC_GTX_CLK125
CLKIN/PCI_CLK duty cycle
CLKIN/PCI_CLK jitter
Notes:
1. Caution: The system, core, USB, security, and TSEC must not exceed their respective maximum or minimum operating
2. Rise and fall times for CLKIN/PCI_CLK are measured at 0.4 and 2.7 V.
3. Timing is guaranteed by design and characterization.
4. This represents the total input jitter—short term and long term—and is guaranteed by design.
5. The CLKIN/PCI_CLK driver’s closed loop jitter bandwidth should be < 500 kHz at –20 dB. The bandwidth must be set low to
6. Spread spectrum clocking is allowed with 1% input frequency down-spread at maximum 50 KHz modulation rate regardless
LV
duty cycle can be loosened from 47%/53% as long as the PHY device can tolerate the duty cycle generated by the eTSEC
GTX_CLK. See
reference clock.
frequencies.
allow cascade-connected PLL-based devices to track CLKIN drivers with the specified jitter.
of input frequency.
DD
= 3.3 V.
RESET Initialization
provides the TSEC gigabit reference clocks (EC_GTX_CLK125) AC timing specifications.
TSEC Gigabit Reference Clock Timing
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10
1000Base-T for RGMII, RTBI
Parameter
Section 8.2.2, “RGMII and RTBI AC Timing Specifications
Table 7. CLKIN AC
LV
LV
Table 8. EC_GTX_CLK125 AC Timing Specifications
DD
DD
GMII, TBI
= 2.5 V
= 3.3 V
DD
= 2.5 ± 0.125 mV/ 3.3 V ± 165 mV
t
G125R
t
G125H
Symbol
t
t
G125
G125
Timing Specifications (continued)
—
/t
t
/t
KHK
G125F
G125
/t
—
CLKIN
Min
45
47
—
—
—
—
40
—
for the duty cycle for 10Base-T and 100Base-T
Typical
125
—
—
—
8
DD
—
—
= 2.5 V and from 0.6 and 2.7 V for
±150
Max
0.75
±150
1.0
55
53
—
—
60
Freescale Semiconductor
MHz
Unit
ps
ns
ns
ps
%
%
Notes
4, 5
—
—
3
1
2
2