MPC8343VRAGDB Freescale Semiconductor, MPC8343VRAGDB Datasheet - Page 78

• Manufacturer Part Number: MPC8343VRAGDB
• Description: IC MPU POWERQUICC II 620-PBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8343VRAGDB

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 620-PBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: MPC8349E-MITXE
• Maximum Clock Frequency: 400 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 400MHz
• Embedded Interface Type: I2C, SPI, USB, UART
• Digital Ic Case Style: BGA
• No. Of Pins: 620
• Rohs Compliant: Yes
• Family Name: MPC83xx
• Device Core: PowerQUICC II Pro
• Device Core Size: 32b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2V
• Operating Supply Voltage (max): 1.26V
• Operating Supply Voltage (min): 1.14V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 620
• Package Type: BGA
• For Use With: CWH-PPC-8343N-VX - KIT EVAL SYSTEM QUICCSTART 8248CWH-PPC-8343N-VE - EVALUATION SYSTEM QUICC MPC8343E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Document Revision History
78
Number
Rev.
3
2
1
0
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10
11/2006
8/2006
4/2006
3/2006
Date
Initial public release.
• Updated note in introduction.
• In the features list in Section 1, “Overview,” updated DDR data rate to show 266 MHz for PBGA
• In Table 57, “Suggested PLL Configurations,” added the following row:
• Ref No: 823, SPMF: 1000, Core PLL: 0100011, 400-MHz Device Input Clock Freq: 33, CSB
• In Section 23, “Ordering Information,” replicated note from document introduction.
• Changed all references to revision 2.0 silicon to revision 3.0 silicon.
• Changed number of general purpose parallel I/O pins to 39 in Section 1, “Overview.”
• Changed VIH minimum value in Table 35, “JTAG Interface DC Electrical Characteristics,” to
• In Table 40, “PCI DC Electrical Characteristics,” changed high-level input voltage values to min =
• In Table 44, “PCI DC Electrical Characteristics,” changed high-level input voltage values to min
• In Table 44, “PCI DC Electrical Characteristics,” changed higl-level input voltage values to min = 2
• Updated DDR2 I/O power values in Table 5, “MPC8347EA Typical I/O Power Dissipation.”
•
• Removed Table 20, “Timing Parameters for DDR2-400.”
• Changed ADDR/CMD to ADDR/CMD/MODT in Table 9, “DDR and DDR2 SDRAM Output AC
• Changed Min and Max values for V
• In Table 58, “MPC8343EA (PBGA) Pinout Listing,” and Table 52, “MPC8347EA (PBGA) Pinout
• Table 58, “MPC8343EA (PBGA) Pinout Listing,” in row AVDD3 changed power supply from
parts for all silicon revisions.
Freq: 266, and Core Freq: 400.
OV
2 and max = OV
= 2 and max = OV
and max = OV
Timing Specifications,” rows 2 and 3, and in Figure 2, “DDR SDRAM Output Timing Diagram.
Characteristics.”
Listing,” modified rows for MDICO and MDIC1 signals and added note ‘It is recommended that
MDICO be tied to GRD using an 18 Ω resistor and MCIC1 be tied to DDR power using an 18 Ω
resistor.’
“AVDD3” to ‘—.’
DD
Table 64. Document Revision History (continued)
– 0.3.
DD
DD
+ 0.3; changed low-level input voltage values to min = (–0.3) and max = 0.8.
DD
+ 0.3; changed low-level input voltage values to min = (–0.3) and max = 0.8.
+ 0.3; changed low-level input voltage values to min = (–0.3) and max = 0.8.
Substantive Change(s)
IH
and VIL in Table 40Table 44,“PCI DC Electrical
Freescale Semiconductor