MPC8343VRAGDB Freescale Semiconductor, MPC8343VRAGDB Datasheet - Page 28

• Manufacturer Part Number: MPC8343VRAGDB
• Description: IC MPU POWERQUICC II 620-PBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8343VRAGDB

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 620-PBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: MPC8349E-MITXE
• Maximum Clock Frequency: 400 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 400MHz
• Embedded Interface Type: I2C, SPI, USB, UART
• Digital Ic Case Style: BGA
• No. Of Pins: 620
• Rohs Compliant: Yes
• Family Name: MPC83xx
• Device Core: PowerQUICC II Pro
• Device Core Size: 32b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2V
• Operating Supply Voltage (max): 1.26V
• Operating Supply Voltage (min): 1.14V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 620
• Package Type: BGA
• For Use With: CWH-PPC-8343N-VX - KIT EVAL SYSTEM QUICCSTART 8248CWH-PPC-8343N-VE - EVALUATION SYSTEM QUICC MPC8343E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Ethernet: Three-Speed Ethernet, MII Management
Figure 12
28
At recommended operating conditions with LV
MDC fall time
Notes:
1. The symbols for timing specifications follow the pattern of t
2. This parameter is dependent on the csb_clk speed (that is, for a csb_clk of 267 MHz, the maximum frequency is 8.3 MHz
3. This parameter is dependent on the csb_clk speed (that is, for a csb_clk of 267 MHz, the delay is 70 ns and for a csb_clk of
and t
timing (MD) for the time t
t
relative to the t
is used with the appropriate letter: R (rise) or F (fall).
and the minimum frequency is 1.2 MHz; for a csb_clk of 375 MHz, the maximum frequency is 11.7 MHz and the minimum
frequency is 1.7 MHz).
333 MHz, the delay is 58 ns).
MDDVKH
(first two letters of functional block)(reference)(state)(signal)(state)
symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state (V)
Parameter/Condition
shows the MII management AC timing diagram.
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10
MDC
(Output)
(Input)
MDIO
MDIO
clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention
MDC
Table 30. MII Management AC Timing Specifications (continued)
MDC
Figure 12. MII Management Interface Timing Diagram
from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time. Also,
t
MDCH
DD
t
is 3.3 V ± 10% or 2.5 V ± 5%.
MDDVKH
t
MDC
t
MDKHDX
Symbol
t
MDHF
1
for outputs. For example, t
(first two letters of functional block)(signal)(state)(reference)(state)
t
MDCF
Min
—
t
MDDXKH
t
MDCR
Typ
—
MDKHDX
Max
symbolizes management data
10
Freescale Semiconductor
Unit
ns
for inputs
Notes
—