MPC8343VRAGDB Freescale Semiconductor, MPC8343VRAGDB Datasheet - Page 13

• Manufacturer Part Number: MPC8343VRAGDB
• Description: IC MPU POWERQUICC II 620-PBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8343VRAGDB

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 620-PBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: MPC8349E-MITXE
• Maximum Clock Frequency: 400 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 400MHz
• Embedded Interface Type: I2C, SPI, USB, UART
• Digital Ic Case Style: BGA
• No. Of Pins: 620
• Rohs Compliant: Yes
• Family Name: MPC83xx
• Device Core: PowerQUICC II Pro
• Device Core Size: 32b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2V
• Operating Supply Voltage (max): 1.26V
• Operating Supply Voltage (min): 1.14V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 620
• Package Type: BGA
• For Use With: CWH-PPC-8343N-VX - KIT EVAL SYSTEM QUICCSTART 8248CWH-PPC-8343N-VE - EVALUATION SYSTEM QUICC MPC8343E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.1
Table 9
5.2
Table 10
Freescale Semiconductor
Required assertion time of HRESET or SRESET (input) to activate reset flow
Required assertion time of PORESET with stable clock applied to CLKIN when the
MPC8343EA is in PCI host mode
Required assertion time of PORESET with stable clock applied to PCI_SYNC_IN
when the MPC8343EA is in PCI agent mode
HRESET/SRESET assertion (output)
HRESET negation to SRESET negation (output)
Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:2] and
CFG_CLKIN_DIV) with respect to negation of PORESET when the MPC8343EA is
in PCI host mode
Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:2] and
CFG_CLKIN_DIV) with respect to negation of PORESET when the MPC8343EA is
in PCI agent mode
Input hold time for POR configuration signals with respect to negation of HRESET
Time for the MPC8343EA to turn off POR configuration signals with respect to the
assertion of HRESET
Input high voltage
Input low voltage
Input current
Output high voltage
Output low voltage
Output low voltage
Notes:
1. This table applies for pins PORESET, HRESET, SRESET, and QUIESCE.
2. HRESET and SRESET are open drain pins, thus V
provides the DC electrical characteristics for the RESET pins of the MPC8343EA.
provides the reset initialization AC timing specifications of the MPC8343EA.
RESET DC Electrical Characteristics
RESET AC Electrical Characteristics
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10
2
Parameter
Table 10. RESET Initialization Timing Specifications
Table 9. RESET Pins DC Electrical Characteristics
Parameter
OH
Symbol
is not relevant for those pins.
V
V
V
V
V
I
OH
OL
IN
OL
IH
IL
I
OH
I
I
OL
OL
Condition
= –8.0 mA
= 8.0 mA
= 3.2 mA
—
—
—
Min
512
32
32
32
16
—
4
4
0
–0.3
Min
2.0
2.4
—
—
—
1
Max
—
—
—
—
—
—
—
—
4
OV
DD
Max
t
t
t
t
t
0.8
0.5
0.4
±5
PCI_SYNC_IN
PCI_SYNC_IN
PCI_SYNC_IN
PCI_SYNC_IN
PCI_SYNC_IN
—
RESET Initialization
+ 0.3
t
t
CLKIN
CLKIN
Unit
ns
ns
Unit
μA
Notes
V
V
V
V
V
—
1
2
1
1
1
2
1
3
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