MPC8343VRAGDB Freescale Semiconductor, MPC8343VRAGDB Datasheet - Page 40

IC MPU POWERQUICC II 620-PBGA

MPC8343VRAGDB

Manufacturer Part Number
MPC8343VRAGDB
Description
IC MPU POWERQUICC II 620-PBGA
Manufacturer
Freescale Semiconductor
Series
PowerQUICC II PROr
Datasheet

Specifications of MPC8343VRAGDB

Processor Type
MPC83xx PowerQUICC II Pro 32-Bit
Speed
400MHz
Voltage
1.2V
Mounting Type
Surface Mount
Package / Case
620-PBGA
Processor Series
MPC8xxx
Core
e300
Data Bus Width
32 bit
Development Tools By Supplier
MPC8349E-MITXE
Maximum Clock Frequency
400 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
I/o Voltage
1.8 V, 2.5 V, 3.3 V
Minimum Operating Temperature
0 C
Core Size
32 Bit
Program Memory Size
64KB
Cpu Speed
400MHz
Embedded Interface Type
I2C, SPI, USB, UART
Digital Ic Case Style
BGA
No. Of Pins
620
Rohs Compliant
Yes
Family Name
MPC83xx
Device Core
PowerQUICC II Pro
Device Core Size
32b
Frequency (max)
400MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
1.2V
Operating Supply Voltage (max)
1.26V
Operating Supply Voltage (min)
1.14V
Operating Temp Range
0C to 105C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
620
Package Type
BGA
For Use With
CWH-PPC-8343N-VX - KIT EVAL SYSTEM QUICCSTART 8248CWH-PPC-8343N-VE - EVALUATION SYSTEM QUICC MPC8343E
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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I
12 I
This section describes the DC and AC electrical characteristics for the I
12.1
Table 38
12.2
Table 39
refer to V
40
At recommended operating conditions with OV
2
Input high voltage level
Input low voltage level
Low level output voltage
Output fall time from V
capacitance from 10 to 400 pF
Pulse width of spikes which must be suppressed by the
input filter
Input current each I/O pin (input voltage is between
0.1 × OV
Capacitance for each I/O pin
Notes:
1. Output voltage (open drain or open collector) condition = 3 mA sink current.
2. C
3. Refer to the MPC8349EA Integrated Host Processor Family Reference Manual, for information on the digital filter used.
4. I/O pins obstruct the SDA and SCL lines if OV
SCL clock frequency
Low period of the SCL clock
High period of the SCL clock
Setup time for a repeated START condition
Hold time (repeated) START condition (after this period, the first clock
pulse is generated)
Data setup time
Data hold time:CBUS compatible masters
I
C
2
C bus devices
B
= capacitance of one bus line in pF.
DD
2
provides the AC timing parameters for the I
provides the DC electrical characteristics for the I
IH
I
I
C
2
and 0.9 × OV
2
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10
(min) and V
C AC Electrical Specifications
C DC Electrical Characteristics
IH
Parameter
(min) to V
DD
(max)
IL
Parameter
(max) levels (see
IL
(max) with a bus
Table 38. I
Table 39. I
DD
of 3.3 V ± 10%.
DD
2
2
C DC Electrical Characteristics
C AC Electrical Specifications
is switched off.
Table
38).
Symbol
t
t
2
I2KHKL
I2KLKV
V
C interface of the MPC8343EA. Note that all values
V
V
C
I
OL
IH
IL
I
I
2
C interface of the MPC8343EA.
20 + 0.1 × C
0.7 × OV
Symbol
t
t
t
t
I2SVKH
I2DVKH
I2DXKL
I2SXKL
t
t
I2CH
f
I2CL
–0.3
Min
I2C
–10
0
0
1
DD
B
2
C interface of the MPC8343EA.
OV
0.3 × OV
0.2 × OV
Min
100
1.3
0.6
0.6
0.6
0
DD
0
Max
250
2
50
10
10
+ 0.3
DD
DD
Freescale Semiconductor
Max
0.9
400
Unit
μA
pF
ns
ns
V
V
V
3
Notes
Unit
kHz
μs
μs
μs
μs
μs
ns
1
2
3
4

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