MPC8343VRAGDB Freescale Semiconductor, MPC8343VRAGDB Datasheet - Page 61

• Manufacturer Part Number: MPC8343VRAGDB
• Description: IC MPU POWERQUICC II 620-PBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8343VRAGDB

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 620-PBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: MPC8349E-MITXE
• Maximum Clock Frequency: 400 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 400MHz
• Embedded Interface Type: I2C, SPI, USB, UART
• Digital Ic Case Style: BGA
• No. Of Pins: 620
• Rohs Compliant: Yes
• Family Name: MPC83xx
• Device Core: PowerQUICC II Pro
• Device Core Size: 32b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2V
• Operating Supply Voltage (max): 1.26V
• Operating Supply Voltage (min): 1.14V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 620
• Package Type: BGA
• For Use With: CWH-PPC-8343N-VX - KIT EVAL SYSTEM QUICCSTART 8248CWH-PPC-8343N-VE - EVALUATION SYSTEM QUICC MPC8343E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1
2
3
4
Table 53
conditions.
19.1
The system PLL is controlled by the RCWL[SPMF] parameter.
encodings for the system PLL.
Freescale Semiconductor
e300 core frequency (core_clk)
Coherent system bus frequency (csb_clk)
DDR1 memory bus frequency (MCK)
DDR2 memory bus frequency (MCK)
Local bus frequency (LCLKn)
PCI input frequency (CLKIN or PCI_CLK)
Security core maximum internal operating frequency
USB_DR, USB_MPH maximum internal operating
frequency
The CLKIN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen so that the resulting csb_clk, MCLK,
LCLK[0:2], and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies. The value
of SCCR[ENCCM], SCCR[USBDRCM], and SCCR[USBMPHCM] must be programmed so that the maximum internal
operating frequency of the Security core and USB modules does not exceed the respective values listed in this table.
The DDR data rate is 2× the DDR memory bus frequency.
The DDR data rate is 2× the DDR memory bus frequency.
The local bus frequency is ½, ¼, or 1/8 of the lbiu_clk frequency (depending on LCCR[CLKDIV]) which is in turn 1× or 2× the
csb_clk frequency (depending on RCWL[LBIUCM]).
provides the operating frequencies for the MPC8343EA PBGA under recommended operating
System PLL Configuration
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10
Parameter
4
1
Table 54. System PLL Multiplication Factors
RCWL[SPMF]
2
3
Table 53. Operating Frequencies for PBGA
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
System PLL Multiplication Factor
266 MHz
200–266
Reserved
× 16
× 10
× 2
× 3
× 4
× 5
× 6
× 7
× 8
× 9
Table 54
16.67–133
333 MHz
200–333
100–266
100–133
100–133
25–66
133
133
shows the multiplication factor
400 MHz
200–400
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Clocking
Unit
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