MPC8343VRAGDB Freescale Semiconductor, MPC8343VRAGDB Datasheet - Page 64

• Manufacturer Part Number: MPC8343VRAGDB
• Description: IC MPU POWERQUICC II 620-PBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8343VRAGDB

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 620-PBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: MPC8349E-MITXE
• Maximum Clock Frequency: 400 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 400MHz
• Embedded Interface Type: I2C, SPI, USB, UART
• Digital Ic Case Style: BGA
• No. Of Pins: 620
• Rohs Compliant: Yes
• Family Name: MPC83xx
• Device Core: PowerQUICC II Pro
• Device Core Size: 32b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2V
• Operating Supply Voltage (max): 1.26V
• Operating Supply Voltage (min): 1.14V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 620
• Package Type: BGA
• For Use With: CWH-PPC-8343N-VX - KIT EVAL SYSTEM QUICCSTART 8248CWH-PPC-8343N-VE - EVALUATION SYSTEM QUICC MPC8343E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1
2
DDR2 memory may be used at 133 MHz provided that the memory components are specified for operation at this frequency.
Clocking
19.2
RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300
core clock (core_clk).
not listed in
64
CFG_CLKIN_DIV doubles csb_clk if set high.
CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode.
CFG_CLKIN_DIV
0–1
nn
00
01
10
11
00
01
10
11
at Reset
High
High
High
High
High
High
Core PLL Configuration
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10
Table 57
RCWL[COREPLL]
1
Core VCO frequency = core frequency × VCO divider
VCO divider must be set properly so that the core VCO frequency is in the
range of 800–1800 MHz.
0000
0001
0001
0001
0001
0001
0001
0001
0001
2–5
should be considered as reserved.
Table 56. CSB Frequency Options for Agent Mode (continued)
Table 57
SPMF
0011
0100
0101
0110
0111
1000
shows the encodings for RCWL[COREPLL]. COREPLL values that are
Table 57. e300 Core PLL Configuration
6
n
0
0
0
0
1
1
1
1
(PLL off, csb_clk clocks core directly)
Input Clock Ratio
csb_clk :
core_clk : csb_clk Ratio
10 : 1
12 : 1
14 : 1
16 : 1
6 : 1
8 : 1
NOTE
PLL bypassed
1.5:1
1.5:1
1.5:1
1.5:1
1:1
1:1
1:1
1:1
2
16.67
100
133
166
200
233
266
Input Clock Frequency (MHz)
csb_clk Frequency (MHz)
(PLL off, csb_clk clocks core directly)
150
200
250
300
25
VCO Divider
PLL bypassed
Freescale Semiconductor
33.33
200
266
333
2
4
8
8
2
4
8
8
1
2
66.67