MC68MH360EM25L Freescale Semiconductor, MC68MH360EM25L Datasheet - Page 189

• Manufacturer Part Number: MC68MH360EM25L
• Description: IC MPU QUICC ETHER 25MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Freescale Semiconductor, Inc.
CPU32+
Interrupt recognition and subsequent processing are based on internal interrupt request sig-
nals (IRQ7–IRQ1) and the current priority set in SR priority mask I2–I0. Interrupt request
level 0 (IRQ7–IRQ1 negated) indicates that no service is requested. When an interrupt of
level 1 through 6 is requested via IRQ6–IRQ1, the processor compares the request level
with the interrupt mask to determine whether the interrupt should be processed. Interrupt
requests are inhibited for all priority levels less than or equal to the current priority. Level 7
interrupts are nonmaskable.
IRQ7–IRQ1 are synchronized and debounced by input circuitry on two consecutive rising
edges of the processor clock.
Interrupt requests do not force immediate exception processing, but are left pending. A
pending interrupt is detected between instructions or at the end of exception processing—
all interrupt requests must be held asserted until they are acknowledged by the CPU. If the
priority of the interrupt is greater than the current priority level, exception processing begins.
Exception processing occurs as follows. First, the processor makes an internal copy of the
SR. After the copy is made, the processor state bits in the SR are changed—the S-bit is set,
establishing supervisor access level, and bits T1 and T0 are cleared, disabling
tracing. Priority level is then set to the level of the interrupt, and the processor fetches a vec-
tor number from the interrupting device (CPU space $F). The fetch bus cycle is classified as
an interrupt acknowledge, and the encoded level number of the interrupt is placed on the
address bus.
If an interrupting device requests automatic vectoring, the processor generates a vector
number (25 to 31) determined by the interrupt level number.
If the response to the interrupt acknowledge bus cycle is a bus error, the interrupt is taken
to be spurious, and the spurious interrupt vector number (24) is generated.
The exception vector number, PC, and SR are saved on the supervisor stack. The saved
value of the PC is the address of the instruction that would have executed if the interrupt had
not occurred.
Priority level 7 interrupt is a special case. Level 7 interrupts are nonmaskable interrupts
(NMI). IRQ7 is a level sensitive input and must remain low until CPU32+ returns a n interrupt
acknowledge cycle for level 7 interrupt.
Many M68000 peripherals provide for programmable interrupt vector numbers to be used in
the system interrupt request/acknowledge mechanism. If the vector number is not initialized
after reset and if the peripheral must acknowledge an interrupt request, the peripheral
should return the uninitialized interrupt vector number (15).
See Section 4 Bus Operation for detailed information on interrupt acknowledge cycles.
5.5.2.12 RETURN FROM EXCEPTION. When exception stacking operations for all pend-
ing exceptions are complete, the processor begins execution of the handler for the last
exception processed. After the exception handler has executed, the processor must restore
MOTOROLA
MC68360 USER’S MANUAL
5-47
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