MC68MH360EM25L Freescale Semiconductor, MC68MH360EM25L Datasheet - Page 938

• Manufacturer Part Number: MC68MH360EM25L
• Description: IC MPU QUICC ETHER 25MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Freescale Semiconductor, Inc.
MC68MH360 Product Brief
D.2.5 Data Flow
In a time slot environment like T1/E1, every slot occupies 8 consecutive bits creating a basic
channel speed of 64 kbit/s. The number of time slots vary depending upon what interface
will be used.
The QUICC32 can support up to 32 time slots with up to 8 bits, each giving a total throughput
of 2.048 Mbit/s for the QMC protocol in a E1 or CEPT interface.
Through the SI RAM, the user programs either to route the whole serial stream to the SCC
dedicated to QMC or use the SI RAM to gate only the designated time slots to the SCC. In
this later case other serial channels in the QUICC32 can be multiplexed to the same physical
interface through the SI RAM routing. External devices can also be used in designated time
slots as long as they do not collide with the internal QUICC32 channels.
Any logical channel can be spread over several time slots creating super channels. The
maximum configuration is to concatenate all 32 time slots into one 2,048 MBit/s channel.
Sub channels are achieved by masking out any combination of the 8 bits in every time slot.
The resulting channel speed is N x 8 Kbit/S {N= 1....8}.
The physical interface from the QUICC32 is routed through the time slot assigner. Each log-
ical channel can work in full duplex mode but does not have to be routed to the same
receiver and transmitter time slot. This is how the standard QUICC operates today with each
of the SCC and SMC channels. The QUICC32 can have independent receive and transmit
clocks as well as frame synchronization signals. All receive and transmit channels within the
QMC will have the same clock.
For diagnostic purpose each logical channel has a local loopback option. The whole incom-
ing TDM frame can be selected to operate in global echo mode. For these diagnostic modes
the clock and synchronization signals must be common for the receiver and transmitter.
D.2.6 Data Management
Time slots are numbered 0 - 31, and each time slot is 8 bits long. The parameter RAM is
divided into a global section and a channel specific section. In the global section the channel
routing is described in two tables, one for transmission and one for reception. This allows
the user to connect the physical time slots to logical channels in any order desired and also
mask for sub channels or to concatenate for super channels. Whatever combination is cho-
sen, the maximum number of supported transmit channels is 32 and the maximum number
of supported receive channels is 32.
For each logical channel there is a channel specific area in the DP RAM that governs the
data flow. For each channel the user can choose if data is transparent or is framed with the
HDLC protocol, and what checksum algorithm is used.
These two areas in the DP RAM occupy the whole space. Therefore the buffer descriptors
for each logical channel have been moved out into the main memory. The buffer descriptors
for all other protocols remain unchanged in internal memory. Depending on how many QMC
channels are used, the space for buffer descriptors in the dual-port memory may vary.
D-8
MC68360 USER’S MANUAL
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com