MC68MH360EM25L Freescale Semiconductor, MC68MH360EM25L Datasheet - Page 724

• Manufacturer Part Number: MC68MH360EM25L
• Description: IC MPU QUICC ETHER 25MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Freescale Semiconductor, Inc.
Applications
9.1.1.10 DOUBLE BUS FAULT. The QUICC double bus fault monitor may be used in the
design. No additional hardware is required.
9.1.1.11 JTAG AND THREE-STATE. The QUICC provides a JTAG test access port, com-
monly known as JTAG. This interface uses five pins: TMS, TDI, TDO, TCK, and TRST. TMS
and TDI are left unconnected because they have internal pullups. The JTAG port is disabled
in this application; however, the capability could be easily added.
When the QUICC is in master mode, it provides a pin (TRIS) that allows all outputs on the
device to be three-stated. This pin is simply pulled high in this application.
9.1.1.12 QUICC SERIAL PORTS. The functions on QUICC parallel I/O ports A, B, and C
may be used as desired in this application, and have no bearing on the design as shown.
However, any unused parallel I/O pins should be configured as outputs so they are not left
floating.
9.1.2 Memory Interfaces
In this application, a number of memory arrays have been developed for EPROM, flash
EPROM, SRAM, EEPROM, and DRAM. Each memory interface can be attached to the sys-
tem bus as desired.
One issue not discussed is the decision of whether external buffers are needed on the sys-
tem bus. This issue depends on the number of memory arrays used in the design and the
layout (i.e., capacitance) of the system bus. This issue is left to the user for his particular
design.
Another issue left to the user is the number of wait states used with each memory system.
This depends on the memory speed, whether external buffers are used, and the loading on
the system bus pins. (The QUICC provides capacitance de-rating figures to calculate the
effect of additional or less capacitance on the AC Timing Specifications.)
9.1.2.1 QUICC MEMORY INTERFACE PINS. In this design, a number of QUICC pins are
made available to the memory arrays (see Figure 9-1). Eight chip select or RAS pins are
available in the system. In this design, CS0 is used for any of the EPROM arrays since this
is the global (boot) chip select. RAS1 is used for the DRAM arrays because of its double-
drive capability. CS2/RAS2 is not used in the design and is available for other purposes,
such as a second DRAM bank. CS3 is for SRAM; CS4 is for EEPROM. CS5, CS6, and CS7
are unused.
Parity may be supported for both SRAM and DRAM arrays using the 4-byte parity lines
PRTY3–PRTY0. In this design, it is shown with only a DRAM. The QUICC is configured in
software to generate a bus error when a parity error occurs.
The QUICC provides the address multiplexing for the DRAM arrays internally, which is con-
figured in software. Therefore, the address multiplex pin is not needed, and it can be used
as its other function—an output enable (OE) pin. The DRAM arrays require the four CAS3–
CAS0 pins provided by the QUICC. The QUICC also provides four write enable (WE) pins
to select the correct byte during write operations.
9-4
MC68360 USER’S MANUAL
MOTOROLA
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