MC68MH360EM25L Freescale Semiconductor, MC68MH360EM25L Datasheet - Page 300

• Manufacturer Part Number: MC68MH360EM25L
• Description: IC MPU QUICC ETHER 25MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Freescale Semiconductor, Inc.
System Integration Module (SIM60)
6.11 GENERAL-PURPOSE CHIP-SELECT OVERVIEW (SRAM BANKS)
Any memory bank that is not used to control DRAM may be used as a general-purpose chip
select, including pins CS0–CS7. This bank is called an SRAM bank. These pins may be
used to support external memory such as SRAM, EPROM, flash EPROM, EEPROM, and
peripherals.
The SRAM banks also have some unique features not available in the DRAM banks. First,
upon system reset, a global (boot) chip select is available. This provides a boot ROM chip
select before the system is fully configured. Second, the SRAM banks offer two-clock
accesses to external SRAM. Finally, each SRAM bank supports a choice of the port size of
its memory or peripheral to be 8, 16, or 32 bits with proper DSACK generation for those port
sizes. Thus, an 8-bit EPROM may be used with a 32-bit SRAM, etc.
6.11.1 Associated Registers
The general-purpose chip selects are controlled by the global memory register (GMR) and
the memory controller status register (MSTAT). There is one GMR and MSTAT in the mem-
ory controller. Additionally, each SRAM bank has a base register (BR) and an option register
(OR).
The GMR is used to control global parameters for both SRAM and DRAM banks.
The MSTAT reports write protect violations and parity errors for both SRAM and DRAM
banks.
The BR and the OR for each of the general-purpose chip selects program most of the fea-
tures. The BR contains a valid (V) bit to indicate that the register information for that chip
select is valid.
6.11.2 8-, 16-, and 32-Bit Port Size Configuration
The general-purpose chip selects support dynamic bus sizing. Defined 8-bit ports are acces-
sible on both odd and even addresses when connected to data bus bits 31–24; defined 16-
bit ports can be accessed as odd bytes, even bytes, or even words when connected to data
bus bits 31–16; and defined 32-bit ports can be accessed as odd bytes, even bytes, odd
words, and even words or long words on long-word boundaries. The port size is specified
by the SPS bits in the OR.
6.11.3 Write Protect Configuration
The WP bit in each BR can restrict write access to its range of addresses. Any attempt to
write this area will result in the WPER bit being set in the MSTAT.
6.11.4 Programmable Wait State Configuration
The general-purpose chip selects support internal DSACKx generation. They allow fast two-
clock accesses to external memory by an internal bus master; from zero-wait-state
accesses (3 clocks) up to 14-wait-state accesses (17 clocks) are allowed for internal bus
masters. For external bus masters, two-clock accesses are not allowed, but 14 wait states
may be programmed. Additionally, if the EMWS bit is set in the GMR, the chip selects can
6-56
MC68360 USER’S MANUAL
MOTOROLA
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