MC68MH360EM25L Freescale Semiconductor, MC68MH360EM25L Datasheet - Page 794

• Manufacturer Part Number: MC68MH360EM25L
• Description: IC MPU QUICC ETHER 25MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Applications
The loop is repeated as long as the test condition is false and the counter D0 is more than
–1. The test condition can be set to always produce a false prior to entering the loop since
the MOVE instructions do not set any flags. Assuming a 40-ns clock, this code loop has
approximately a 500-kHz test clock frequency.
The state machine is static, and all logic can be clocked between DC and the maximum
device frequency. Additionally, there are no constraints on the clock duty cycle.
All inputs are sampled on the rising clock edge. Data must be valid during a setup time
before the transition and a hold time after transition. Different input pins have different
requirements, depending on whether they belong to the TAP or are normal I/O pins. Output
pins change state on the falling clock edge and can be either high, low, or three-state. The
exact I/O pin timings can be found in the AC Timing Specifications of this manual.
The repeat pattern in Figure 9-26 is created to meet these requirements. In row 8, the data
write pattern is stable, and only the TCK pin changes state from 0 to 1. The data write pattern
in row 9 sets up the data pattern for the next 0 to 1 clock transition and changes the current
clock state back to 0, thus enabling the TDO signal out of the external device. The data read
pattern in row 9 reads the TDO into the microprocessor memory array, where it can be com-
pared against the expected value.
9.8 INTERFACING AN MC68EC030 MASTER TO THE QUICC IN SLAVE
The following paragraphs describe the interface to the QUICC using an MC68EC030 to
replace the CPU32+ core on the QUICC. When the CPU32+ core on the QUICC is disabled,
the QUICC is in slave mode. In slave mode, another external processor may be used
instead of the on-chip CPU32+ core. The QUICC, however, has special features for provid-
ing a glueless interface to an external MC68EC030 (as well as other M68030 and M68040
family members).
The following paragraphs discuss both the hardware and software issues concerning this
solution in a system that contains one MC68EC030 and one QUICC. It is also possible to
interface more than one QUICC to an MC68EC030.
9.8.1 MC68EC030 to QUICC Interface
The following paragraphs discuss the hardware and software issues relating to the connec-
tion between the MC68EC030 and the QUICC. The features of the QUICC that may be used
to assist the MC68EC030 are also detailed. Reference Figure 9-27 during this discussion.
9-74
MODE
LOOPMOVE.B(A0)+, (A1)WRITE ROW 8
MOVE.B(A0)+,(A1)WRITE ROW 9
MOVE.B(A1),(A2)+READ ROW 9
(Next, compare TDO read value to TDO of pattern and
take desired action if the results do not match)
DBcc
D0,LOOP
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