MC68MH360EM25L Freescale Semiconductor, MC68MH360EM25L Datasheet - Page 578

• Manufacturer Part Number: MC68MH360EM25L
• Description: IC MPU QUICC ETHER 25MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Serial Communication Controllers (SCCs)
into one of 64 bins. The 64 bins are represented by 64 bits stored in GADDR1–4 or IADDR1–
4.
When the SET GROUP ADDRESS command is executed, the Ethernet controller maps the
selected 48-bit address into one of the 64 bits. This is performed by passing the 48-bit
address through the on-chip 32-bit CRC generator and selecting 6 bits of the CRC-encoded
result to generate a number between 1 and 64. Bits 31–30 of the CRC result select one of
the four GADDRs or IADDRs, and bits 29–26 of the CRC result select the bit within the
selected register.
When a frame is received by the Ethernet controller, the same process is used. If the CRC
generator selects a bit that is set in the group/individual hash table, the frame is accepted;
otherwise, it is rejected. The result is that if eight group addresses are stored in the hash
table, and random group addresses are received, the hash table prevents roughly 56/64 (or
87.5%) of the group address frames from reaching memory. Those that do reach memory
must be further filtered by the processor to determine if they truly contain one of the eight
desired addresses.
Better performance is achieved by using the group hash table and individual hash table at
the same time. For instance, if eight group and eight physical addresses are stored in their
respective hash tables, 87.5% of all frames (not just group address frames) are prevented
from reaching memory.
The effectiveness of the hash table declines as the number of addresses increases. For
instance, with 128 addresses stored in a 64-bin hash table, the vast majority of the hash
table bits will be set, preventing only a small fraction of the frames from reaching memory.
In such instances, an external CAM is advised if the extra bus utilization cannot be tolerated.
See 7.10.23.7 CAM Interface for more details.
7.10.23.13 INTERPACKET GAP TIME. The minimum interpacket gap time for back-to-
back transmission is 9.6 s. The receiver can receive back-to-back frames with this mini-
mum spacing. In addition, after the backoff algorithm, the transmitter will wait for carrier
sense to be negated before retransmitting the frame. The retransmission will begin 9.6 s
after carrier sense is negated if carrier sense stays negated for at least 6.4 s.
7.10.23.14 COLLISION HANDLING. If a collision occurs during frame transmission, the
Ethernet controller will continue the transmission for at least 32 bit times, transmitting a JAM
pattern consisting of 32 ones. If the collision occurs during the preamble sequence, the JAM
pattern will be sent after the end of the preamble sequence.
If a collision occurs within 64 byte times, the retry process is initiated. The transmitter will
wait a random number of slot times. A slot time is 512 bit times (52 s). If collision occurs
7-254
The hash tables cannot be used to reject frames that match a set
of entered addresses because unintended addresses will be
mapped to the same bit in the hash table. Thus, an external
CAM must be used to implement this function.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE
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