MC68MH360EM25L Freescale Semiconductor, MC68MH360EM25L Datasheet - Page 212

• Manufacturer Part Number: MC68MH360EM25L
• Description: IC MPU QUICC ETHER 25MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

CPU32+
5-70
Read A/D Register
Write A/D Register
Read System Register
Write System Register
Read Memory Location
Write Memory Location
Dump Memory Block
Fill Memory Block
Resume Execution
Call User Code
Reset Peripherals
No Operation
Command
COMMANDS TRANSMITTED TO THE CPU32
RESPONSES FROM THE CPU
READ (LONG)
???
RESULTS FROM PREVIOUS COMMAND
COMMAND CODE TRANSMITTED DURING THIS CYCLE
WAREG/WDREG The data operand is written to the specified address or data register.
RAREG/RDREG Read the selected address or data register and return the results via the se-
SEQUENCE TAKEN IF
ILLEGAL COMMAND
IS RECEIVED BY CPU32
Mnemonic
"NOT READY"
Figure 5-27. Command Sequence Diagram
WSREG
MS ADDR
"ILLEGAL"
WRITE
DUMP
READ
CALL
NOP
FILL
RST
XXX
GO
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Table 5-23. BDM Command Summary
For More Information On This Product,
HIGH-ORDER 16 BITS OF MEMORY ADDRESS
MC68360 USER’S MANUAL
rial interface.
The specified system control register is read. All registers that can be read
in supervisor mode can be read in BDM.
The operand data is written into the specified system control register.
Read the sized data at the memory location specified by the long-word ad-
dress. The SFC register determines the address space accessed.
Write the operand data to the memory location specified by the long-word
address. The DFC register determines the address space accessed.
Used in conjunction with the READ command to dump large blocks of mem-
ory. An initial READ is executed to set up the starting address of the block
and to retrieve the first result. Subsequent operands are retrieved with the
DUMP command.
Used in conjunction with the WRITE command to fill large blocks of memory.
An initial WRITE is executed to set up the starting address of the block and
to supply the first operand. Subsequent operands are written with the FILL
command.
The pipeline is flushed and refilled before resuming instruction execution at
the return PC.
Current PC is stacked at the location of the current SP. Instruction execution
begins at user patch code.
Asserts RESET for 512 clock cycles. The CPU is not reset by this command.
Synonymous with the CPU RESET instruction.
NOP performs no operation and may be used as a null command.
DATA UNUSED FROM
THIS TRANSFER
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"NOT READY"
"NOT READY"
NEXT CMD
LS ADDR
LOW-ORDER 16 BITS OF MEMORY ADDRESS
LOCATION
MEMORY
READ
NONSERIAL-RELATED ACTIVITY
Description
HIGH- AND LOW-ORDER
16 BITS OF RESULT
SEQUENCE TAKEN IF
OPERATION HAS NOT
COMPLETED
SEQUENCE TAKEN IF BUS ERROR
OR ADDRESS ERROR OCCURS ON
MEMORY ACCESS
"NOT READY"
MS RESULT
BERR/AERR
XXX
XXX
XXX
XXX
"NOT READY"
COMMAND
NEXT CMD
LS RESULT
NEXT CMD
NEXT
CODE
MOTOROLA