MC68MH360EM25L Freescale Semiconductor, MC68MH360EM25L Datasheet - Page 64

• Manufacturer Part Number: MC68MH360EM25L
• Description: IC MPU QUICC ETHER 25MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Signal Descriptions
2-16
Group
SMC
BRG
SPI
PIP
SDMA
SI
SPI Master-In Slave-
SMC Transmit Data SMTXD2–SMTXD1 Serial data output from the SMCs. (O)
Baud Rate Genera-
SMC Receive Data SMRXD2–SMRXD1 Serial data input to the SMCs. (I)
SI Transmit Clock L1TCLKA, L1TCLKB Input transmit clock to TDM channel A or channel B.
SI Transmit Data
SI Receive Clock
IDL Interface Re-
BRG Input Clock
SI Receive Data
SDMA Acknowl-
SI Output Clock
SI Data Strobes
SPI Master-Out
Signal Name
Timer Output
Sync Signals
Sync Signals
Port B 15–0
SI Transmit
tor Out 4–1
SI Receive
Strobe Out
SPI Select
SMC Sync
SPI Clock
Strobe In
edge 2–1
Slave-In
quest
Out
Table 2-8. Peripherals Signal Index (Continued)
SMSYN2–SMSYN1 SMC synchronization signal. (I)
SDACK2–SDACK1 SDMA output signals used in RISC receiver to mark fields in the
L1RXDA, L1RXDB Serial input to the time division multiplexed (TDM) channel A or
L1TXDA, L1TXDB Serial output from the TDM channel A or channel B.
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BRGO4–BRGO1 Baud rate generator output clock allows baud rate generator to be
TOUT4–TOUT1
L1RQA, L1RQB
L1ST4– L1ST1
L1RSYNCA,
CLK2, CLK6
For More Information On This Product,
L1TSYNCA,
L1RSYNCB
L1TSYNCB
Mnemonic
PB15–PB0
L1RCLKA,
L1CLKOA,
L1RCLKB
L1CLKOB
SPIMISO
SPIMOSI
SPICLK
SPISEL
STRBO
STRBI
MC68360 USER’S MANUAL
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Output waveform (pulse or toggle) from the timer as a result of a ref-
erence value being reached. (O)
Serial data input to the SPI master (I); serial data output from an SPI
slave (O).
Serial data output from the SPI master (O).; serial data input to an
SPI slave (I).
Output clock from the SPI master (O); input clock to the SPI slave (I).
SPI slave select input. (I)
channel B.
Input receive clock to TDM channel A or channel B.
Input transmit data sync signal to the TDM channel A or channel B.
Input receive data sync signal to TDM channel A or channel B.
IDL interface request to transmit on the D channel. Output from the
SI.
Output serial data rate clock. Can output a data rate clock when the
input clock is 2x the data rate.
Serial data strobe outputs can be used to gate clocks to external de-
vices that do not have a built-in time slot assigner (TSA).
used externally.
Baud rate generator input clock from which BRG will derive the baud
rates.
PIP Data I/O Pins
This input causes the PIP output data to be placed on the PIP data
pins.
This input causes data on the PIP data pins to be latched by the PIP
as input data.
Ethernet receive frame.
Function
MOTOROLA