MC68MH360EM25L Freescale Semiconductor, MC68MH360EM25L Datasheet - Page 58

• Manufacturer Part Number: MC68MH360EM25L
• Description: IC MPU QUICC ETHER 25MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Freescale Semiconductor, Inc.
Signal Descriptions
BCLRO—This active-low open-drain output indicates that one of the QUICC internal bus
masters is requesting the external bus master to release the bus.
CONFIG1—See 2.1.13 Initial Configuration Pins (CONFIG) for the description.
RAS2—See 2.1.5.1 Chip Select/Row Address Select (CS6–CS0/RAS6–RAS0) for the
description.
2.1.9 System Control Signals
The QUICC uses these signals to recover from an exception. Refer to Section 4 Bus Oper-
ation for more information on these signals.
2.1.9.1 SOFT RESET (RESETS). This active-low, open-drain, bidirectional signal is used to
initiate reset. An external reset signal (as well as a reset from the SIM60) resets the QUICC
as well as all external devices. A reset signal from the CPU32+ (asserted as part of the
RESET instruction) resets external devices only—the internal state of the CPU32+ is not
affected; other on-chip modules are reset, but the configuration is not altered. When
asserted by the QUICC, this signal is guaranteed to be asserted for a minimum of 512 clock
cycles. For more information see 4.7 Reset Operation.
2.1.9.2 HARD RESET (RESETH). This active-low, open-drain, bidirectional signal is used
to initiate reset. An external hard reset signal (as well as an hard reset from the SIM60)
resets the QUICC as well as all external devices and the internal state of the CPU32+; other
on-chip modules are reset as well as the QUICC configuration. When asserted by the
QUICC, this signal is guaranteed to be asserted for a minimum of 512 clock cycles. For more
information see 4.7 Reset Operation.
During a hard reset, the address, data, and bus control pins are all three-stated. The BG pin
output is the same as that on the BR input. The general-purpose I/O pins are all configured
as inputs. The NC4–NC1 pins are undefined outputs. The XTAL, CLKO1, and CLKO2 pins
are active outputs, except for CLKO1 which does not oscillate while the on-chip PLL is
attaining a lock. The RESETS pin is an output.
2.1.9.3 HALT (HALT). This active-low, open-drain, bidirectional signal is asserted to sus-
pend external bus activity, to request a retry when used with BERR, or to perform a single-
step operation. As an output, HALT indicates a double bus fault by the CPU32+.
2.1.9.4 BUS ERROR (BERR). This active-low, open-drain, bidirectional signal indicates
that an invalid bus operation is being attempted or, when used with HALT, that the bus mas-
ter should retry the current cycle.
2.1.10 Clock Signals
These signals are used by the QUICC for controlling or generating the system clocks. Refer
to Section 6 System Integration Module (SIM60) for more information on these clock signals.
2.1.10.1 SYSTEM CLOCK OUTPUTS (CLKO2–CLKO1). These output signals reflect the
general system clock and are used as the bus timing reference by external devices. CLKO1
2-10
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MOTOROLA
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