MC68MH360EM25L Freescale Semiconductor, MC68MH360EM25L Datasheet - Page 771

• Manufacturer Part Number: MC68MH360EM25L
• Description: IC MPU QUICC ETHER 25MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Applications
9.4.4 Interfacing Multiple QUICCs to an MC68EC040
It is possible to interface multiple QUICCs to an MC68EC040. The first QUICC can be con-
figured as previously shown in this subsection. Additional QUICCs should be configured as
noted in the following list:
9.5 SELECTING CACHE MODES ON THE MC68EC040
When the QUICC is used in its MC68040 companion mode with the MC68040, it is recom-
mended that the QUICC serial data buffers be cache inhibited by the MC68040. This avoids
the overhead that would result from the cache coherency algorithms of the MC68040 follow-
ing the frequent write accesses by the QUICC to one of its serial data buffers located in
external memory. When using the MC68040, the MC68040 memory management unit
(MMU) may be used to cache inhibit the data buffers. However, the lower cost MC68EC040
does not have an MMU. Therefore, what technique can be used by the MC68EC040 to
cache inhibit serial data buffers? The following paragraphs discuss a method for selecting
caching modes on 16-byte boundaries for an MC68EC040.
The MC68EC040 delivers high performance at a low system cost for embedded control by
providing the same high integer performance and large 4K instruction/data caches as the
MC68040 without the floating-point unit and MMU. The MC68040 MMU makes the caching
9-51
BCYC1–BCYC0 may be set to zeros (no wait states) if the QUICC is controlling the burst-
ing for the MC68EC040 and the timing supports one-clock MC68EC040 bursting. Howev-
er, with 60- or 70-ns DRAMs at 25 MHz, BCYC1–BCYC0 should be set to 01 for two-clock
MC68EC040 bursting.
PGME should be cleared.
SPS1–SPS0 should be cleared.
DSSEL should be set only if this is a DRAM bank.
• The additional QUICCs should have their CONFIG2–CONFIG0 pins configured for
• The MBAR of the additional QUICCs should be programmed using the MBARE pin and
• An external bus arbiter is required to take the bus request of the additional QUICC
• An external interrupt prioritizer is required to determine which QUICC IOUT2–IOUT0
• The additional QUICCs should not be configured to perform any memory controller sup-
slave mode, global chip select disabled , and MBAR at $003FF04. These QUICCs still
recognize and respond to MC68040 cycles via the TS pin, even though their CONFIG2–
CONFIG0 pins are not configured for MC68040 companion mode.
MBARE register as described in Section 6 System Integration Module (SIM60).
(which is an output because of the CONFIG2–CONFIG0 pins) and prioritize it with the
MC68EC040, present it to the original QUICC, and issue a bus grant to the appropriate
device.
pins are currently routed to the MC68EC040. Alternatively, the additional QUICC
should have its interrupts brought out on a single RQOUT pin, which is routed to one of
the original QUICC interrupt inputs. This would eliminate the external logic.
port functions for the MC68EC040. Only the original QUICC should be used for this pur-
pose.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
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