MC68MH360EM25L Freescale Semiconductor, MC68MH360EM25L Datasheet - Page 376

• Manufacturer Part Number: MC68MH360EM25L
• Description: IC MPU QUICC ETHER 25MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

IDMA Channels
If the IDMA has obtained the IMB and is also waiting to obtain the external bus, but the exter-
nal bus master performs an access to a location internal to the QUICC, the IDMA will relin-
quish the IMB and retry the cycle once it has obtained the IMB.
7.6.4.8 ENDING THE IDMA TRANSFER. If no bus exceptions occur, the IDMA eventually
finishes the transfer of a block of data. These paragraphs describe normal termination in
more detail. (Termination by error is discussed in 7.6.4.7.2 Bus Error.)
The IDMA channel operation experiences normal termination when the BCR is decre-
mented to zero or the external device signals a termination of the transfer using DONEx.
These terminations are independent of how requests are generated to the IDMA.
Additionally, the user may stop the IDMA channel by clearing STR. However, this is consid-
ered a suspension of activity, rather than normal termination, since the transfer resumes
when STR is set once again.
The user may also terminate the transfer by setting the RST bit in the CMR; however, this
is not a normal termination of IDMA activity.
Further description of normal termination depends on the mode of the IDMA: single buffer
mode, auto buffer mode, and buffer chaining. These modes are described in the following
paragraphs.
7.6.4.8.1 Single Buffer Mode Termination. The following methods may be used to termi-
nate an IDMA transfer in the single buffer mode. They may also be used to terminate a cur-
rent BD transfer in the auto buffer and buffer chaining modes.
Transfer Count Exhausted. When the channel performs an operand transfer, it decre-
ments the BCR for each byte transferred successfully. When the BCR is decremented to
zero, the transfer is terminated. When the last bus cycle of the transfer occurs (either a byte,
word, or long-word access), DONEx is asserted during that bus cycle. If the device is the
source, further destination accesses will take place after DONEx is asserted. If the device
is the destination, DONEx will be asserted on the final bus cycle of the destination write.
When the operand transfer has completed and the BCR has been decremented to zero, the
channel operation is terminated, STR is cleared, and a DONE bit interrupt is generated if the
corresponding CMAR bit is set. The SAPR and/or DAPR are also incremented in the normal
fashion.
7-52
This behavior of DONEx also applies to memory-to-memory
transfers. DONEx is asserted on either the last source or desti-
nation bus cycle, as determined by the ECO bit in the CMR.
If the channel was started with the BCR value set to zero, the
channel will transfer 4 Gbytes before the transfer count is ex-
hausted.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE
NOTE
MOTOROLA