MC68MH360EM25L Freescale Semiconductor, MC68MH360EM25L Datasheet - Page 691

• Manufacturer Part Number: MC68MH360EM25L
• Description: IC MPU QUICC ETHER 25MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

The port C lines associated with the CDx and CTSx pins have a mode of operation where
the pin may be internally connected to the SCC but may also generate interrupts. Port C still
detects changes on the CTS and CD pins and asserts the corresponding interrupt request,
but the SCC simultaneously uses the CTS and/or CD pin to automatically control operation.
This allows the user to fully implement protocols V.24, X.21, and X.21 bis (with the assis-
tance of other general-purpose I/O lines).
To configure a port C pin as a CTS or CD pin that is connected to the SCC and also gener-
ates interrupts, use the following steps:
7.14.10 Port C Registers
The user interfaces with port C via five registers. The port C interrupt control register
(PCINT) indicates how changes on the pin cause interrupts when interrupts are generated
with that pin. The port C special options register (PCSO) indicates whether certain port C
pins have the ability to be connected to on-chip peripherals while simultaneously being able
to generate an interrupt. The other three port C registers also exist on the other ports:
PCDAT, PCDIR, and PCPAR. Since port C does not have open-drain capability, it does not
contain an open-drain register.
MOTOROLA
4. Set the PCINT bit to determine which edges cause interrupts.
5. Write the corresponding CIMR bit with a one to allow interrupts to be generated to the
6. Read the pin value using the PCDAT.
1. Write the corresponding PCPAR bit with a zero.
2. Write the corresponding PCDIR bit with a zero.
3. Write the corresponding PCSO bit with a one.
4. Set the PCINT bit to determine which edges cause interrupts.
5. Write the corresponding CIMR bit with a one to allow interrupts to be generated to the
6. The pin value may be read at any time using PCDAT.
CPU32+ core.
CPU32+ core.
These steps correspond to the “software operation” mode of the
SCM DIAG bits on the MC68302.
After connecting the CTS or CD pins to the SCC, the user must
also choose the “normal operation” mode in DIAG bits of the
general SCC mode register (GSMR) to enable and disable SCC
transmission and reception with these pins.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE
NOTE
Parallel I/O Ports
7-367