PIC16F726-I/SP Microchip Technology Inc., PIC16F726-I/SP Datasheet - Page 112
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PIC16F726-I/SP
Manufacturer Part Number
PIC16F726-I/SP
Description
28 PIN, 14 KB FLASH, 1.8V-5.5V, 16 MHZ INT. OSC.
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F726-ISP.pdf
(266 pages)
Specifications of PIC16F726-I/SP
A/d Inputs
11-Channel, 8-Bit
Comparators
2
Cpu Speed
5 MIPS
Eeprom Memory
0 Bytes
Frequency
20 MHz
Input Output
25
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SPDIP
Programmable Memory
14K Bytes
Ram Size
368 Bytes
Resistance, Drain To Source On
Bytes
Serial Interface
I2C, SPI, AUSART
Speed
20 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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PIC16F72X/PIC16LF72X
11.1.3
A single software programmable prescaler is available
for use with either Timer0 or the Watchdog Timer
(WDT), but not both simultaneously. The prescaler
assignment is controlled by the PSA bit of the OPTION
register. To assign the prescaler to Timer0, the PSA bit
must be cleared to a ‘0’.
There are 8 prescaler options for the Timer0 module
ranging from 1:2 to 1:256. The prescale values are
selectable via the PS<2:0> bits of the OPTION register.
In order to have a 1:1 prescaler value for the Timer0
module, the prescaler must be assigned to the WDT
module.
The prescaler is not readable or writable. When
assigned to the Timer0 module, all instructions writing to
the TMR0 register will clear the prescaler.
11.1.4
Timer0 will generate an interrupt when the TMR0
register overflows from FFh to 00h. The T0IF interrupt
flag bit of the INTCON register is set every time the
TMR0 register overflows, regardless of whether or not
the Timer0 interrupt is enabled. The T0IF bit can only
be cleared in software. The Timer0 interrupt enable is
the T0IE bit of the INTCON register.
11.1.5
When in 8-Bit Counter Mode, the incrementing edge on
the T0CKI pin must be synchronized to the instruction
clock. Synchronization can be accomplished by
sampling the prescaler output on the Q2 and Q4 cycles
of the instruction clock. The high and low periods of the
external clocking source must meet the timing
requirements as shown in Section 23.0 “Electrical
Specifications”.
DS41341B-page 110
Note:
Note:
SOFTWARE PROGRAMMABLE
PRESCALER
When the prescaler is assigned to WDT, a
CLRWDT instruction will clear the prescaler
along with the WDT.
TIMER0 INTERRUPT
The Timer0 interrupt cannot wake the
processor from Sleep since the timer is
frozen during Sleep.
8-BIT COUNTER MODE
SYNCHRONIZATION
Preliminary
© 2008 Microchip Technology Inc.
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