PIC16F726-I/SP Microchip Technology Inc., PIC16F726-I/SP Datasheet - Page 134

• Manufacturer Part Number: PIC16F726-I/SP
• Description: 28 PIN, 14 KB FLASH, 1.8V-5.5V, 16 MHZ INT. OSC.
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F726-I/SP

• A/d Inputs: 11-Channel, 8-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Frequency: 20 MHz
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 14K Bytes
• Ram Size: 368 Bytes
• Resistance, Drain To Source On: Bytes
• Serial Interface: I2C, SPI, AUSART
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F72X/PIC16LF72X
REGISTER 14-2:
TABLE 14-2:
41341B-page 132
ANSELA
ANSELB
ANSELD
OPTION_REG
PIE1
PIR1
T1CON
T2CON
TRISA
TRISB
TRISD
Legend:
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-4
bit 3-0
Note 1:
Name
U-0
—
2:
- = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the capacitive sensing module.
These channels are not implemented on the PIC16F722/723/726/PIC16LF722/723/726.
This bit is not implemented on PIC16F722/723/726/PIC16LF722/723/726, Read as ‘0’
TMR1CS1
TMR1GIE
TMR1GIF
TRISA7
TRISB7
TRISD7
ANSD7
RBPU
Bit 7
Unimplemented: Read as ‘0’
CPSCH<3:0>: Capacitive Sensing Channel Select bits
If CPSON = 0:
If CPSON = 1:
—
—
—
SUMMARY OF REGISTERS ASSOCIATED WITH CAPACITIVE SENSING
These bits are ignored. No channel is selected.
U-0
0000 = channel 0, (CPS0)
0001 = channel 1, (CPS1)
0010 = channel 2, (CPS2)
0011 = channel 3, (CPS3)
0100 = channel 4, (CPS4)
0101 = channel 5, (CPS5)
0110 = channel 6, (CPS6)
0111 = channel 7, (CPS7)
1000 = channel 8, (CPS8
1001 = channel 9, (CPS9
1010 = channel 10, (CPS10
1011 = channel 11, (CPS11
1100 = channel 12, (CPS12
1101 = channel 13, (CPS13
1110 = channel 14, (CPS14
1111 = channel 15, (CPS15
—
CPSCON1: CAPACITIVE SENSING CONTROL REGISTER 1
TMR1CS0
TOUTPS3
INTEDG
TRISD6
TRISA6
TRISB6
ANSD6
ADIE
ADIF
Bit 6
—
—
W = Writable bit
‘1’ = Bit is set
TOUTPS2
T1CKPS1
TRISD5
TRISA5
TRISB5
ANSA5
ANSB5
ANSD5
T0CS
U-0
RCIE
RCIF
Bit 5
—
TOUTPS1
T1CKPS0
TRISA4
TRISB4
TRISD4
ANSD4
ANSA4
ANSB4
T0SE
Bit 4
TXIE
TXIF
(1)
(1)
U-0
(1)
)
)
(1)
(1)
(1)
(1)
(1)
Preliminary
—
)
)
)
)
)
)
T1OSCEN
TOUTPS0
TRISA3
TRISB3
TRISD3
ANSD3
ANSA3
ANSB3
SSPIE
SSPIF
Bit 3
PSA
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
CPSCH3
R/W-0
TMR2ON
T1SYNC
CCP1IE
CCP1IF
TRISA2
TRISB2
TRISD2
ANSA2
ANSB2
ANSD2
Bit 2
PS2
(2)
T2CKPS1
TMR2IE
TMR2IF
TRISA1
TRISB1
TRISD1
ANSA1
ANSB1
ANSD1
CPSCH2
Bit 1
PS1
R/W-0
—
T2CKPS0
TMR1ON
TMR1IE
TMR1IF
TRISD0
TRISA0
TRISB0
ANSA0
ANSB0
ANSD0
Bit 0
© 2008 Microchip Technology Inc.
PS0
x = Bit is unknown
CPSCH1
R/W-0
--11 1111
--11 1111
1111 1111
1111 1111
0000 0000
0000 0000
0000 00-0
-000 0000
1111 1111
1111 1111
1111 1111
POR, BOR
Value on
CPSCH0
--11 1111
--11 1111
1111 1111
1111 1111
0000 0000
0000 0000
0000 00-0
-000 0000
1111 1111
1111 1111
1111 1111
R/W-0
Value on
all other
Resets
bit 0