PIC16F726-I/SP Microchip Technology Inc., PIC16F726-I/SP Datasheet - Page 177

• Manufacturer Part Number: PIC16F726-I/SP
• Description: 28 PIN, 14 KB FLASH, 1.8V-5.5V, 16 MHZ INT. OSC.
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F726-I/SP

• A/d Inputs: 11-Channel, 8-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Frequency: 20 MHz
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 14K Bytes
• Ram Size: 368 Bytes
• Resistance, Drain To Source On: Bytes
• Serial Interface: I2C, SPI, AUSART
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

17.2
The SSP module, in I
functions, except general call support. It provides
interrupts on Start and Stop bits in hardware to facilitate
firmware implementations of the master functions. The
SSP module implements the I
specifications:
• I
• I
• Start and Stop bit interrupts enabled to support
• Address masking
Two pins are used for data transfer; the SCL pin (clock
line) and the SDA pin (data line). The user must
configure the two pin's data direction bits as inputs in
the appropriate TRIS register. Upon enabling I
mode, the I
controlled by the SMP bit of SSPSTAT register. The
SSP module functions are enabled by setting the
SSPEN bit of SSPCON register.
Data is sampled on the rising edge and shifted out on
the falling edge of the clock. This ensures that the SDA
signal is valid during the SCL high time. The SCL clock
input must have minimum high and low times for proper
operation.
Specifications”.
FIGURE 17-7:
© 2008 Microchip Technology Inc.
firmware Master mode
2
2
C Slave mode (7-bit address)
C Slave mode (10-bit address)
SDA
SCL
I
2
C Mode
2
C slew rate limiters in the I/O pads are
Refer
Read
Shift
Clock
MSb
to
2
I
DIAGRAM
2
C mode, implements all slave
SSPMSK Reg
SSPADD Reg
Match Detect
C™ MODE BLOCK
Stop bit Detect
SSPBUF Reg
SSPSR Reg
Section 23.0
Start and
2
C Standard mode
LSb
Write
Addr Match
Internal
Data Bus
“Electrical
Preliminary
2
C
PIC16F72X/PIC16LF72X
FIGURE 17-8:
The SSP module has six registers for I
They are:
• SSP Control (SSPCON) register
• SSP Status (SSPSTAT) register
• Serial Receive/Transmit Buffer (SSPBUF) register
• SSP Shift Register (SSPSR), not directly
• SSP Address (SSPADD) register
• SSP Address Mask (SSPMSK) register
17.2.1
Selection of I
SSPCON register set, forces the SCL and SDA pins to
be open drain, provided these pins are programmed as
inputs by setting the appropriate TRISC bits. The SSP
module will override the input state with the output data,
when required, such as for Acknowledge and
slave-transmitter sequences.
accessible
Note:
Master
HARDWARE SETUP
Pull-up
externally to the SCL and SDA pins for
proper operation of the I
SDA
SCL
2
C mode, with the SSPEN bit of the
V
resistors
TYPICAL I
CONNECTIONS
DD
V
DD
must
2
DS41341B-page 175
C™
2
C module.
SDA
SDA
SCL
SCL
(optional)
Slave 1
Slave 2
be
2
C operation.
provided