PIC16F726-I/SP Microchip Technology Inc., PIC16F726-I/SP Datasheet - Page 26

• Manufacturer Part Number: PIC16F726-I/SP
• Description: 28 PIN, 14 KB FLASH, 1.8V-5.5V, 16 MHZ INT. OSC.
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F726-I/SP

• A/d Inputs: 11-Channel, 8-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Frequency: 20 MHz
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 14K Bytes
• Ram Size: 368 Bytes
• Resistance, Drain To Source On: Bytes
• Serial Interface: I2C, SPI, AUSART
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F72X/PIC16LF72X
TABLE 2-1:
DS41341B-page 24
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
Legend:
Note
Address
Bank 2
Bank 3
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(3)
(1, 2)
(2)
(1, 2)
(2)
1:
2:
3:
4:
5:
6:
INDF
TMR0
PCL
STATUS
FSR
CPSCON0
CPSCON1
PCLATH
INTCON
PMDATL
PMADRL
PMDATH
PMADRH
INDF
OPTION_REG
PCL
STATUS
FSR
ANSELA
ANSELB
ANSELD
ANSELE
PCLATH
INTCON
PMCON1
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are
transferred to the upper byte of the program counter.
These registers can be addressed from any bank.
These registers/bits are not implemented on PIC16F722/723/726/PIC16LF722/723/726 devices, read as ‘0’.
Accessible only when SSPM<3:0> = 1001.
Accessible only when SSPM<3:0> ≠ 1001.
This bit is always ‘1’ as RE3 is input only.
Name
—
—
—
—
—
—
—
PIC16F72X/PIC16LF72X SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 Module Register
Program Counter’s (PC) Least Significant Byte
Indirect Data Memory Address Pointer
Unimplemented
Unimplemented
Unimplemented
Program Memory Read Data Register Low Byte
Program Memory Read Address Register Low Byte
Addressing this location uses contents of FSR to address data memory (not a physical register)
Program Counter (PC) Least Significant Byte
Indirect Data Memory Address Pointer
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Reserved
CPSON
ANSD7
RBPU
Bit 7
GIE
GIE
IRP
IRP
—
—
—
—
—
—
—
—
INTEDG
ANSD6
PEIE
PEIE
Bit 6
RP1
RP1
—
—
—
—
—
—
—
—
—
—
Program Memory Read Data Register High Byte
ANSD5
ANSA5
ANSB5
T0CS
Bit 5
T0IE
T0IE
RP0
RP0
—
—
—
—
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
Program Memory Read Address Register High Byte
Write Buffer for the upper 5 bits of the Program Counter
Preliminary
ANSA4
ANSB4
ANSD4
T0SE
Bit 4
INTE
INTE
TO
TO
—
—
—
—
CPSRNG1 CPSRNG0
CPSCH3
ANSA3
ANSB3
ANSD3
RBIE
RBIE
Bit 3
PSA
PD
PD
—
—
CPSCH2
ANSA2
ANSB2
ANSD2
ANSE2
Bit 2
T0IF
T0IF
PS2
—
Z
Z
CPSOUT
CPSCH1
ANSA1
ANSB1
ANSD1
ANSE1
Bit 1
INTF
INTF
PS1
DC
DC
—
© 2008 Microchip Technology Inc.
CPSCH0
ANSD0
T0XCS
ANSA0
ANSB0
ANSE0
Bit 0
RBIF
RBIF
PS0
RD
C
C
xxxx xxxx
xxxx xxxx
0000 0000
0001 1xxx
xxxx xxxx
0--- 0000
---- 0000
---0 0000
0000 000x
xxxx xxxx
xxxx xxxx
--xx xxxx
---x xxxx
xxxx xxxx
1111 1111
0000 0000
0001 1xxx
xxxx xxxx
--11 1111
--11 1111
1111 1111
---- -111
---0 0000
0000 000x
1--- ---0
POR, BOR
Value on:
—
—
—
—
—
—
—
109,38
131,39
132,39
187,39
187,39
187,39
187,39
188,39
29,38
28,38
25,38
29,38
28,38
44,38
29,38
26,39
28,38
25,38
29,38
53,39
62,39
79,39
84,39
28,38
44,38
Page
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