PIC16F726-I/SP Microchip Technology Inc., PIC16F726-I/SP Datasheet - Page 113
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PIC16F726-I/SP
Manufacturer Part Number
PIC16F726-I/SP
Description
28 PIN, 14 KB FLASH, 1.8V-5.5V, 16 MHZ INT. OSC.
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F726-ISP.pdf
(266 pages)
Specifications of PIC16F726-I/SP
A/d Inputs
11-Channel, 8-Bit
Comparators
2
Cpu Speed
5 MIPS
Eeprom Memory
0 Bytes
Frequency
20 MHz
Input Output
25
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SPDIP
Programmable Memory
14K Bytes
Ram Size
368 Bytes
Resistance, Drain To Source On
Bytes
Serial Interface
I2C, SPI, AUSART
Speed
20 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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REGISTER 11-1:
TABLE 11-1:
© 2008 Microchip Technology Inc.
CPSCON0
INTCON
OPTION_REG
TMR0
TRISA
Legend:
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
R/W-1
RBPU
Name
– = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Timer0 module.
Timer0 Module Register
CPSON
TRISA7
RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of INT pin
0 = Interrupt on falling edge of INT pin
T0CS: TMR0 Clock Source Select bit
1 = Transition on T0CKI pin or CPSOSC signal
0 = Internal instruction cycle clock (F
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
PS<2:0>: Prescaler Rate Select bits
RBPU
Bit 7
GIE
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0
INTEDG
R/W-1
OPTION_REG: OPTION REGISTER
INTEDG
TRISA6
PEIE
BIT VALUE
Bit 6
—
000
001
010
011
100
101
110
111
W = Writable bit
‘1’ = Bit is set
R/W-1
T0CS
TRISA5
T0CS
Bit 5
T0IE
—
TMR0 RATE
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
TRISA4
T0SE
Bit 4
INTE
—
R/W-1
T0SE
Preliminary
WDT RATE
CPSRNG1 CPSRNG0
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
OSC
TRISA3
RBIE
Bit 3
PSA
PIC16F72X/PIC16LF72X
/4)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-1
PSA
TRISA2
Bit 2
T0IF
PS2
CPSOUT
TRISA1
Bit 1
INTF
PS1
R/W-1
PS2
TRISA0
T0XCS
RBIF
Bit 0
PS0
x = Bit is unknown
R/W-1
0--- 0000
0000 000x
1111 1111
xxxx xxxx
1111 1111
POR, BOR
PS1
Value on
DS41341B-page 111
0--- 0000
0000 000x
1111 1111
uuuu uuuu
1111 1111
R/W-1
Value on
all other
PS0
Resets
bit 0
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