PIC16F726-I/SP Microchip Technology Inc., PIC16F726-I/SP Datasheet - Page 163
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PIC16F726-I/SP
Manufacturer Part Number
PIC16F726-I/SP
Description
28 PIN, 14 KB FLASH, 1.8V-5.5V, 16 MHZ INT. OSC.
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F726-ISP.pdf
(266 pages)
Specifications of PIC16F726-I/SP
A/d Inputs
11-Channel, 8-Bit
Comparators
2
Cpu Speed
5 MIPS
Eeprom Memory
0 Bytes
Frequency
20 MHz
Input Output
25
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SPDIP
Programmable Memory
14K Bytes
Ram Size
368 Bytes
Resistance, Drain To Source On
Bytes
Serial Interface
I2C, SPI, AUSART
Speed
20 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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16.3.2
The following bits are used to configure the AUSART
for Synchronous slave operation:
• SYNC = 1
• CSRC = 0
• SREN = 0 (for transmit); SREN = 1 (for receive)
• CREN = 0 (for transmit); CREN = 1 (for receive)
• SPEN = 1
Setting the SYNC bit of the TXSTA register configures the
device for synchronous operation. Clearing the CSRC bit
of the TXSTA register configures the device as a slave.
Clearing the SREN and CREN bits of the RCSTA register
ensures that the device is in the Transmit mode,
otherwise the device will be configured to receive. Setting
the SPEN bit of the RCSTA register enables the
AUSART.
16.3.2.1
The operation of the Synchronous Master and Slave
modes
“Synchronous Master Transmission”), except in the
case of the Sleep mode.
TABLE 16-8:
© 2008 Microchip Technology Inc.
INTCON
PIE1
PIR1
RCSTA
TRISC
TXREG
TXSTA
Legend:
Name
are
x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Slave Transmission.
SYNCHRONOUS SLAVE MODE
AUSART Transmit Data Register
TMR1GIE
TMR1GIF
TRISC7
AUSART Synchronous Slave
Transmit
SPEN
CSRC
Bit 7
identical
GIE
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
TRISC6
PEIE
ADIE
ADIF
Bit 6
RX9
TX9
(refer
TRISC5
to
SREN
TXEN
RCIE
RCIF
Bit 5
T0IE
Section 16.3.1.2
TRISC4
CREN
SYNC
Bit 4
INTE
TXIE
TXIF
Preliminary
ADDEN
TRISC3
SSPIE
SSPIF
RBIE
Bit 3
PIC16F72X/PIC16LF72X
—
CCP1IE
CCP1IF
TRISC2
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
1.
2.
3.
4.
5.
16.3.2.2
1.
2.
3.
4.
5.
6.
7.
8.
BRGH
FERR
Bit 2
T0IF
The first character will immediately transfer to
the TSR register and transmit.
The second word will remain in TXREG register.
The TXIF bit will not be set.
After the first character has been shifted out of
TSR, the TXREG register will transfer the second
character to the TSR and the TXIF bit will now be
set.
If the PEIE and TXIE bits are set, the interrupt
will wake the device from Sleep and execute the
next instruction. If the GIE bit is also set, the
program will call the Interrupt Service Routine.
Set the SYNC and SPEN bits and clear the
CSRC bit.
Clear the CREN and SREN bits.
If using interrupts, ensure that the GIE and PEIE
bits of the INTCON register are set and set the
TXIE bit.
If 9-bit transmission is desired, set the TX9 bit.
Enable transmission by setting the TXEN bit.
Verify address detection is disabled by clearing
the ADDEN bit of the RCSTA register.
If 9-bit transmission is selected, insert the Most
Significant bit into the TX9D bit.
Start
Significant 8 bits to the TXREG register.
TMR2IE
TMR2IF
TRISC1
OERR
TRMT
Bit 1
INTF
transmission
Synchronous Slave Transmission
Set-up:
TMR1IE
TMR1IF
TRISC0
RX9D
TX9D
Bit 0
RBIF
by
0000 000x
0000 0000
0000 0000
0000 000X
1111 1111
0000 0000
0000 -010
POR, BOR
Value on
writing
DS41341B-page 161
the
0000 000x
0000 0000
0000 0000
0000 000X
1111 1111
0000 0000
0000 -010
Value on
all other
Resets
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