PIC16F726-I/SP Microchip Technology Inc., PIC16F726-I/SP Datasheet - Page 193
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PIC16F726-I/SP
Manufacturer Part Number
PIC16F726-I/SP
Description
28 PIN, 14 KB FLASH, 1.8V-5.5V, 16 MHZ INT. OSC.
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F726-ISP.pdf
(266 pages)
Specifications of PIC16F726-I/SP
A/d Inputs
11-Channel, 8-Bit
Comparators
2
Cpu Speed
5 MIPS
Eeprom Memory
0 Bytes
Frequency
20 MHz
Input Output
25
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SPDIP
Programmable Memory
14K Bytes
Ram Size
368 Bytes
Resistance, Drain To Source On
Bytes
Serial Interface
I2C, SPI, AUSART
Speed
20 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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19.0
The Power-down mode is entered by executing a
SLEEP instruction.
If the Watchdog Timer is enabled:
• WDT will be cleared but keeps running.
• PD bit of the STATUS register is cleared.
• TO bit of the STATUS register is set.
• Oscillator driver is turned off.
• Timer1 oscillator is unaffected
• I/O ports maintain the status they had before
For lowest current consumption in this mode, all I/O
pins should be either at V
circuitry drawing current from the I/O pin. I/O pins that
are high-impedance inputs should be pulled high or low
externally to avoid switching currents caused by float-
ing inputs. The T0CKI input should also be at V
V
from on-chip pull-ups on PORTB should be considered.
The MCLR pin must be at a logic high level when
external MCLR is enabled.
19.1
The device can wake-up from Sleep through one of the
following events:
1.
2.
3.
The first event will cause a device Reset. The two latter
events are considered a continuation of program
execution. The TO and PD bits in the STATUS register
can be used to determine the cause of device Reset.
The PD bit, which is set on power-up, is cleared when
Sleep is invoked. TO bit is cleared if WDT wake-up
occurred.
© 2008 Microchip Technology Inc.
SS
SLEEP was executed (driving high, low or high-
impedance).
Note:
External Reset input on MCLR pin.
Watchdog
enabled).
Interrupt from RB0/INT pin, PORTB change or a
peripheral interrupt.
for lowest current consumption. The contribution
POWER-DOWN MODE (SLEEP)
Wake-up from Sleep
A Reset generated by a WDT time-out
does not drive MCLR pin low.
Timer
wake-up
DD
or V
SS
(if
, with no external
WDT
was
DD
Preliminary
or
PIC16F72X/PIC16LF72X
The following peripheral interrupts can wake the device
from Sleep:
1.
2.
3.
4.
5.
6.
7.
Other peripherals cannot generate interrupts since
during Sleep, no on-chip clocks are present.
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is prefetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction, then branches to the interrupt
address (0004h). In cases where the execution of the
instruction following SLEEP is not desirable, the user
should have a NOP after the SLEEP instruction.
The WDT is cleared when the device wakes up from
Sleep, regardless of the source of wake-up.
Note:
TMR1 Interrupt. Timer1 must be operating as an
asynchronous counter.
USART Receive Interrupt (Synchronous Slave
mode only)
A/D conversion (when A/D clock source is RC)
Interrupt-on-change
External Interrupt from INT pin
Capture event on CCP1 or CCP2
SSP Interrupt in SPI or I
If the global interrupts are disabled (GIE is
cleared), but any interrupt source has both
its interrupt enable bit and the correspond-
ing interrupt flag bits set, the device will
immediately wake-up from Sleep. The
SLEEP instruction is completely executed.
2
C Slave mode
DS41341B-page 191
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