PIC16F726-I/SP Microchip Technology Inc., PIC16F726-I/SP Datasheet - Page 49
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PIC16F726-I/SP
Manufacturer Part Number
PIC16F726-I/SP
Description
28 PIN, 14 KB FLASH, 1.8V-5.5V, 16 MHZ INT. OSC.
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F726-ISP.pdf
(266 pages)
Specifications of PIC16F726-I/SP
A/d Inputs
11-Channel, 8-Bit
Comparators
2
Cpu Speed
5 MIPS
Eeprom Memory
0 Bytes
Frequency
20 MHz
Input Output
25
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SPDIP
Programmable Memory
14K Bytes
Ram Size
368 Bytes
Resistance, Drain To Source On
Bytes
Serial Interface
I2C, SPI, AUSART
Speed
20 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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4.5.4
The PIR1 register contains the interrupt flag bits, as
shown in Register 4-4.
REGISTER 4-4:
© 2008 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
TMR1GIF
R/W-0
PIR1 REGISTER
TMR1GIF: Timer1 Gate Interrupt Flag bit
1 = Timer1 Gate is inactive
0 = Timer1 Gate is active
ADIF: A/D Converter Interrupt Flag bit
1 = A/D conversion complete (must be cleared in software)
0 = A/D conversion has not completed or has not been started
RCIF: USART Receive Interrupt Flag bit
1 = The USART receive buffer is full (cleared by reading RCREG)
0 = The USART receive buffer is not full
TXIF: USART Transmit Interrupt Flag bit
1 = The USART transmit buffer is empty (cleared by writing to TXREG)
0 = The USART transmit buffer is full
SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit
1 = The Transmission/Reception is complete (must be cleared in software)
0 = Waiting to Transmit/Receive
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
Compare mode:
PWM mode:
Unused in this mode
TMR2IF: Timer2 to PR2 Interrupt Flag bit
1 = A Timer2 to PR2 match occurred (must be cleared in software)
0 = No Timer2 to PR2 match occurred
TMR1IF: Timer1 Overflow Interrupt Flag bit
1 = The TMR1 register overflowed (must be cleared in software)
0 = The TMR1 register did not overflow
R/W-0
ADIF
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1
W = Writable bit
‘1’ = Bit is set
RCIF
R-0
TXIF
R-0
Preliminary
PIC16F72X/PIC16LF72X
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
SSPIF
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE of the INTCON register.
User
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
CCP1IF
R/W-0
software
x = Bit is unknown
TMR2IF
R/W-0
should
DS41341B-page 47
ensure
TMR1IF
R/W-0
bit 0
the
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