TDGL003 Microchip Technology, TDGL003 Datasheet - Page 144

• Manufacturer Part Number: TDGL003
• Description: ChipKIT Max32 Development Board PIC32 Boards And Kits
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr
• Type: MCUr

Specifications of TDGL003

• Silicon Manufacturer: Microchip
• Core Architecture: MIPS
• Core Sub-architecture: PIC32
• Silicon Core Number: PIC32MX
• Silicon Family Name: PIC32MX795Fxxxx
• Kit Contents: Board Only
• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: MPLAB®, Arduino™ Mega

PIC32MX3XX/4XX
TABLE 27-1:
DS61143H-page 144
RDPGPR
ROTR
ROTRV
SB
SC
SDBBP
SEB
SEH
SH
SLL
SLLV
SLT
SLTI
SLTIU
SLTU
SRA
SRAV
SRL
SRLV
SSNOP
SUB
SUBU
SW
SWL
SWR
SYNC
SYSCALL
TEQ
TEQI
Note 1:
Instruction
This instruction is deprecated and should not be used.
MIPS32
Read GPR from Previous Shadow Set
Rotate Word Right
Rotate Word Right Variable
Store Byte
Store Conditional Word
Software Debug Break Point
Sign-Extend Byte
Sign-Extend Half
Store Half
Shift Left Logical
Shift Left Logical Variable
Set on Less Than
Set on Less Than Immediate
Set on Less Than Immediate Unsigned
Set on Less Than Unsigned
Shift Right Arithmetic
Shift Right Arithmetic Variable
Shift Right Logical
Shift Right Logical Variable
Superscalar Inhibit No Operation
Integer Subtract
Unsigned Subtract
Store Word
Store Word Left
Store Word Right
Synchronize
System Call
Trap if Equal
Trap if Equal Immediate
®
INSTRUCTION SET (CONTINUED)
Description
Rt = SGPR[SRSCtl
Rd = Rt
Rd = Rt
(byte)Mem[Rs+offset] = Rt
if LL
Rt = LL
Trap to SW Debug Handler
Rd = SignExtend (Rs-7...0)
Rd = SignExtend (Rs-15...0)
(half)Mem[Rs+offset> = Rt
Rd = Rt << sa
Rd = Rt << Rs[4:0]
if (int)Rs < (int)Rt
else
if (int)Rs < (int)Immed
else
if (uns)Rs < (uns)Immed
else
if (uns)Rs < (uns)Immed
else
Rd = (int)Rt >> sa
Rd = (int)Rt >> Rs[4:0]
Rd = (uns)Rt >> sa
Rd = (uns)Rt >> Rs[4:0]
NOP
Rt = (int)Rs - (int)Rd
Rt = (uns)Rs - (uns)Rd
Mem[Rs+offset] = Rt
Mem[Rs+offset] = Rt
Mem[Rs+offset] = Rt
Orders the cached coherent and
uncached loads and stores for access to
the shared memory
SystemCallException
if Rs == Rt
if Rs == (int)Immed
Rd = 1
Rd = 0
Rt = 1
Rt = 0
Rt = 1
Rt = 0
Rd = 1
Rd = 0
TrapException
TrapException
mem[Rs+offset> = Rt
bit
sa-1..0
Rs-1..0
bit
= 1
© 2011 Microchip Technology Inc.
Function
|| Rt
|| Rt
PSS
, Rd]
31..sa
31..Rs