TDGL003 Microchip Technology, TDGL003 Datasheet - Page 95

ChipKIT Max32 Development Board PIC32 Boards And Kits

TDGL003

Manufacturer Part Number
TDGL003
Description
ChipKIT Max32 Development Board PIC32 Boards And Kits
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Type
MCUr
Datasheets

Specifications of TDGL003

Silicon Manufacturer
Microchip
Core Architecture
MIPS
Core Sub-architecture
PIC32
Silicon Core Number
PIC32MX
Silicon Family Name
PIC32MX795Fxxxx
Kit Contents
Board Only
Contents
Board
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
MPLAB®, Arduino™ Mega
9.0
FIGURE 9-1:
© 2011 Microchip Technology Inc.
Note 1: This data sheet summarizes the features
CTRL
2: Some registers and associated bits
PREFETCH CACHE
of the PIC32MX3XX/4XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 4. “Prefetch
Cache” (DS61119) of the “PIC32 Family
Reference Manual”, which is available
from
(www.microchip.com/PIC32).
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
Prefetch Control
Cache Control
Bus Control
Miss LRU
Hit LRU
the
FSM
PREFETCH MODULE BLOCK DIAGRAM
CTRL
Microchip
Tag Logic
Hit Logic
Prefetch
web
PFM
site
in
Address
Encode
Cache
Line
CTRL
Prefetch cache increases performance for applications
executing out of the cacheable program Flash memory
regions by implementing instruction caching, constant
data caching and instruction prefetching.
9.1
• 16 Fully Associative Lockable Cache Lines
• 16-byte Cache Lines
• Up to four Cache Lines Allocated to Data
• Two Cache Lines with Address Mask to hold
• Pseudo LRU replacement policy
• All Cache Lines are software writable
• 16-byte parallel memory fetch
• Predictive Instruction Prefetch
repeated instructions
Cache Line
PIC32MX3XX/4XX
Prefetch
Features
RDATA
RDATA
DS61143H-page 95

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