DSP56002FC66 Freescale Semiconductor, DSP56002FC66 Datasheet - Page 106

• Manufacturer Part Number: DSP56002FC66
• Manufacturer: Freescale Semiconductor

Specifications of DSP56002FC66

• Device Core Size: 24b
• Architecture: Harvard
• Format: Fixed Point
• Clock Freq (max): 66MHz
• Mips: 33
• Device Input Clock Speed: 66MHz
• Ram Size: 3KB
• Program Memory Size: 1.5KB
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Design Considerations
Host Port Considerations
HOST PORT CONSIDERATIONS
Host Programming Considerations
4-6
UNSYNCHRONIZED READING OF RECEIVE BYTE REGISTERS
OVERWRITING TRANSMIT BYTE REGISTERS
SYNCHRONIZATION OF STATUS BITS FROM DSP TO HOST
OVERWRITING THE HOST VECTOR
Careful synchronization is required when reading multibit registers that are written
by another asynchronous system. This is a common problem when two
asynchronous systems are connected. The situation exists in the host interface. The
following paragraphs present considerations for proper operation.
When reading receive byte registers (RXH, RXM, and RXL) the host programmer
should use interrupts or poll the RXDF flag that indicates that data is available. This
assures that the data in the receive byte registers will be stable.
The host programmer should not write to the transmit byte registers (TXH, TXM, and
TXL) unless the TXDE bit is set indicating that the transmit byte registers are empty.
This guarantees that the transmit byte registers will transfer valid data to the HRX
register.
HC, HREQ, DMA, HF3, HF2, TRDY, TXDE, and RXDF status bits are set or cleared
from inside the DSP and read by the host processor. The host can read these status
bits very quickly without regard to the clock rate used by the DSP, but the possibility
exists that the state of the bit could be changing during the read operation. This is
generally not a system problem, since the bit will be read correctly in the next pass of
any host polling routine.
Note: Refer to DSP56002 User’s Manual sections describing the I/O Interface and
The Host programmer should change the Host Vector register only when the Host
Command bit (HC) is clear. This change guarantees that the DSP interrupt control
logic will receive a stable vector.
Host/DMA Interface Programming Model for descriptions of these status
bits.
Freescale Semiconductor, Inc.
For More Information On This Product,
DSP56002/D, Rev. 3
Go to: www.freescale.com
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