DSP56002FC66 Freescale Semiconductor, DSP56002FC66 Datasheet - Page 17

• Manufacturer Part Number: DSP56002FC66
• Manufacturer: Freescale Semiconductor

Specifications of DSP56002FC66

• Device Core Size: 24b
• Architecture: Harvard
• Format: Fixed Point
• Clock Freq (max): 66MHz
• Mips: 33
• Device Input Clock Speed: 66MHz
• Ram Size: 3KB
• Program Memory Size: 1.5KB
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / Rohs Status: Supplier Unconfirmed

MOTOROLA
MODC/NMI
RESET
Signal Name
Table 1-8 Interrupt and Mode Control Signals (Continued)
Signal
Input
Input
Type
Freescale Semiconductor, Inc.
For More Information On This Product,
Input
Input
during
Reset
State
Go to: www.freescale.com
Mode Select C/Non-maskable Interrupt Request—This input
has two functions:
MODC is read and internally latched in the DSP when the
processor exits the Reset state. MODA, MODB, and MODC
select the initial chip operating mode. Several clock cycles
(depending on PLL stabilization time) after leaving the Reset
state, the MODC signal changes to the nonmaskable external
interrupt request NMI. After reset, the chip operating mode
can be changed by software. The NMI input is an external
interrupt request that indicates that an external device is
requesting service. It may be programmed to be level-sensitive
or negative-edge-triggered. If level-sensitive triggering is
selected, an external pull up resistor is required for wired-OR
operation.
Reset—This input is a direct hardware reset on the processor.
When RESET is asserted low, the DSP is initialized and placed
in the Reset state. A Schmitt trigger input is used for noise
immunity. When the RESET signal is deasserted, the initial
chip operating mode is latched from the MODA, MODB, and
MODC signals. The internal reset signal is deasserted
synchronous with the internal clocks. In addition, the PINIT
pin is sampled and written into the PEN bit of the PLL Control
Register and the CKP pin is sampled to determine the polarity
of the CKOUT signal.
DSP56002/D, Rev. 3
1. to select the initial chip operating mode, and
2. after internal synchronization, to allow an external
device to request a non-maskable DSP interrupt.
Signal Description
Interrupt and Mode Control
Signal/Pin Descriptions
1-11