DSP56002FC66 Freescale Semiconductor, DSP56002FC66 Datasheet - Page 43
DSP56002FC66
Manufacturer Part Number
DSP56002FC66
Description
Manufacturer
Freescale Semiconductor
Datasheet
1.DSP56002FC66.pdf
(110 pages)
Specifications of DSP56002FC66
Device Core Size
24b
Architecture
Harvard
Format
Fixed Point
Clock Freq (max)
66MHz
Mips
33
Device Input Clock Speed
66MHz
Ram Size
3KB
Program Memory Size
1.5KB
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temp Range
-40C to 105C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
132
Package Type
PQFP
Lead Free Status / Rohs Status
Supplier Unconfirmed
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSP56002FC66
Manufacturer:
MOTOROLA
Quantity:
5 530
Company:
Part Number:
DSP56002FC66
Manufacturer:
MOTOROLA
Quantity:
6 250
Company:
Part Number:
DSP56002FC66
Manufacturer:
MOTOROLA
Quantity:
591
Part Number:
DSP56002FC66
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
Company:
Part Number:
DSP56002FC661H72G
Manufacturer:
AD
Quantity:
92
SERIAL COMMUNICATION INTERFACE (SCI) TIMING
C
t
Control Register and T
MOTOROLA
SCC
L
= 50 pF + 2 TTL loads
Num
Num
= Synchronous Clock Cycle Time (For internal clock, t
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Synchronous Clock Cycle—t
Clock Low Period
Clock High Period
< intentionally blank >
Output Data Setup to Clock Falling Edge
(Internal Clock)
Output Data Hold After Clock Rising Edge
(Internal Clock)
Input Data Setup Time Before Clock
Rising Edge (Internal Clock)
Input Data Not Valid Before Clock Rising
Edge (Internal Clock)
Clock Falling Edge to Output Data Valid
(External Clock)
Output Data Hold After Clock Rising Edge
(External Clock)
Input Data Setup Time Before Clock
Rising Edge (External Clock)
Input Data Hold Time After Clock Rising
Edge (External Clock)
Asynchronous Clock Cycle—t
Clock Low Period
Clock High Period
< intentionally blank >
Output Data Setup to Clock Rising Edge (Internal
Clock)
Output Data Hold After Clock Rising Edge
(Internal Clock)
Table 2-9 SCI Synchronous Mode Timing (All Frequencies)
Table 2-10 SCI Asynchronous Mode Timing—1X Clock
Freescale Semiconductor, Inc.
C.
Characteristics
For More Information On This Product,
) The minimum t
Characteristics
Go to: www.freescale.com
SCC
DSP56002/D, Rev. 3
ACC
SCC
value is 8 T
t
Serial Communication Interface (SCI) Timing
t
SCC
SCC
t
SCC
t
t
SCC
SCC
/4 + T
/4 + T
/4 – T
T
Min
/2 – 10.5
/2 – 10.5
8T
C
SCC
C
—
—
—
16
21
t
t
t
t
.
ACC
ACC
ACC
ACC
+ 3
C
L
L
64T
is determined by the SCI Clock
L
Min
/2 – 11
/2 – 11
—
/2 – 51
/2 – 51
+ 23
– 26
– 8
C
t
SCC
/4 + T
Max
32.5
—
—
—
—
—
—
—
—
—
—
Max
—
—
—
—
—
—
L
– 5.5
Specifications
Unit
Unit
ns
ns
ns
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
ns
ns
2-17