CN8236EBGB Mindspeed Technologies, CN8236EBGB Datasheet - Page 108

• Manufacturer Part Number: CN8236EBGB
• Description: ATM SAR 155Mbps 3.3V ABR/CBR/GFR/UBR/VBR 388-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8236EBGB

• Package: 388BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 155 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V

Table 4-24. Segmentation Status Queue Base Table Entry
4.0 Segmentation Coprocessor
4.3 Segmentation Control and Data Structures
Table 4-25. Segmentation Status Queue Base Table Entry Field Descriptions
4-30
Word 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BASE_PNTR
LOCAL
SIZE
WRITE
READ_UD
0
1
4.3.6.2 Status Queue
4.3.6.3 Status Queue
Field Name
SIZE
Management
Rsvd
Overflow
Points (Bits 31:2) to base of status queue. Bits 1:0 are always 0 (word-aligned).
0 = Status queue located in PCI address space.
1 = Status queue located in SAR-shared memory address space.
This bit should be set to 0 for a write-only PCI host architecture.
Number of entries in this status queue:
00 = 64
01 = 256
10 = 1,024
11 = 4,096
SAR write pointer. Represents the SAR’s current position in the queue.
Last update of the host processor read pointer. This field is written by the host processor.
At initialization, the host assigns the location and size of up to 32 queues by
initializing internal registers, the segmentation status queue base table entries.
The location and size of each queue is independently programmable via these
base tables.
in the queues with fields in the base table entries. The host manages the queues as
write-only status queues. The status queue base table entry contains all of the
SAR’s write-only control variables.
Since status queues contain a finite number of entries, it is possible that the SAR
will exhaust the available entries. Although the SAR handles this condition, the
host should attempt to prevent overflows.
(WRITE = READ_UD-1), and alerts the host to this condition by setting the
OVFL bit in the status entry. Until the host services the queue and increments the
READ_UD pointer in the base table register, the CN8236 inhibits segmentation
on all channels that report on the overflowed status queue. All other channels are
unaffected.
The SAR tracks its current position and the most recent known host position
Tables 4-24
The CN8236 detects when it writes the last available entry in a status queue
WRITE
Mindspeed Technologies
and
4-25
BASE_PNTR
describe the format of these entries.
ATM ServiceSAR Plus with xBR Traffic Management
Description
Reserved
™
READ_UD
28236-DSH-001-B
CN8236