CN8236EBGB Mindspeed Technologies, CN8236EBGB Datasheet - Page 211

• Manufacturer Part Number: CN8236EBGB
• Description: ATM SAR 155Mbps 3.3V ABR/CBR/GFR/UBR/VBR 388-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8236EBGB

• Package: 388BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 155 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V

CN8236
ATM ServiceSAR Plus with xBR Traffic Management
28236-DSH-001-B
6.4.2.1 Configuring the
Link for GFC Operation
The following example describes a sequence of how to auto-configure a link for
GFC operation after the link has been initialized:
1.
2.
3.
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6.
7.
8.
9.
10.
Host sets a software GFC initialization timer = 0.
Disable reassembly coprocessor by setting RSM_CTRL0(RSM_EN) = 0.
Set the framer chip to pass unassigned cells.
Enable the GFC link interrupt (GFC_LINK) by setting HOST_IMASK0
(EN_GFC_LINK) = 1.
Read HOST_ISTAT0 register twice to clear it.
Enable the reassembly coprocessor and set the GFC initialization timer to
some user-assigned value.
Upon occurrence of an interrupt and before the GFC initialization timer
expires, read HOST_ISTAT0. If GFC_LINK is a logic high, continue. If
the timer expires before GFC_LINK is detected, do not enable the link for
GFC processing.
Set SEG_CTRL(SEG_GFC) to a logic high.
Set the GFCn bit(s) in the SCH_PRI register to enable the appropriate
priority queue(s) for GFC-controlled operation.
Set the framer chip to generate unassigned cells with GFC field in cell
headers set to the value of 0001.
Mindspeed Technologies
™
6.4 GFC Flow Control Manager
6.0 Traffic Management
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