CN8236EBGB Mindspeed Technologies, CN8236EBGB Datasheet - Page 392

• Manufacturer Part Number: CN8236EBGB
• Description: ATM SAR 155Mbps 3.3V ABR/CBR/GFR/UBR/VBR 388-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8236EBGB

• Package: 388BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 155 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V

16.0 Electrical and Mechanical Specifications
16.1 Timing
Table 16-10. Local Processor Memory Interface Timing
16-16
NOTE(S):
(1)
(2)
(3)
Symbol
t
t
pdaenh
t
t
pdaenl
t
t
cwdh
See
In the case of two cycle memory, or when inserting wait states by PWAIT*, MOE*, MWE[3:0]*, and MWR* are extended
across 2 or more clock cycles with the same relative timing to SYSCLK. See the functional timing diagrams in
t
t
cwds
t
t
t
t
t
mcs
t
t
oeh
t
crd
lod
loe
lav
oel
wh
las
be
wl
lav
Figures 16-13
is valid for second and subsequent accesses during burst transfers. See functional timing diagrams.
SYSCLK to PDAEN* Low, Bus Recovery Cycle
SYSCLK to PDAEN* High, Bus Recovery Cycle
LADDR[18:2], LDATA Output Disable to PDAEN* Low,
Bus Recovery Cycle
PDAEN* High to LADDR[18:2], LDATA Output Enable,
Bus Recovery Cycle
SYSCLK to MCS*[3:0] Valid
SYSCLK to LADDR[1,0] Valid
MOE* Active from SYSCLK
MOE* Inactive from SYSCLK
MWR*, MWE[3:0] Active from SYSCLK
MWR*, MWE[3:0]* Inactive to SYSCLK
MWE[3:0]* Byte Enables Valid from SYSCLK (RAMMODE = 1)
CSR Read Data Output Valid
CSR Write Data Setup to SYSCLK
CSR Write Data Hold from SYSCLK
LADDR Setup to SYSCLK
and
16-14
for waveforms and definitions.
(1)
(1)
Parameter
(1, 3)
(1)
(1, 3)
Mindspeed Technologies
(1, 2)
(1, 3)
(1, 3)
(1)
(1)
ATM ServiceSAR Plus with xBR Traffic Management
(1)
™
Min
—
—
—
12
2
4
9
1
1
8
1
1
2
8
0
Max
12
—
—
—
20
10
16
20
—
—
—
6
7
1
7
28236-DSH-001-B
Section
CN8236
Units
10.6.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns