CN8236EBGB Mindspeed Technologies, CN8236EBGB Datasheet - Page 344

• Manufacturer Part Number: CN8236EBGB
• Description: ATM SAR 155Mbps 3.3V ABR/CBR/GFR/UBR/VBR 388-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8236EBGB

• Package: 388BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 155 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V

14.0 CN8236 Registers
14.6 Counters and Status Registers
0x1a8
This register provides the status of the AALx shadow counters. All bits are latched until read. Any bit set to a
logic high causes the AALx_STAT bit to be set in the HOST_ISTAT1 and LP_ISTAT1 registers.
0x1ac—Transmit Port Cell Discard Status Register (TX_STATUS)
This register indicates the status of a PHY device. If the head of line flushing mechanism is enabled
(TX_FIFO_FLUSH_EN set in Configuration register 1), this register indicates if a cell has been discarded due
to the head of line flushing mechanism. If a bit x of the TX_STAT bitmap is set, PHY x discarded a cell. If 1 or
more bits of TX_STAT is set, an interrupt is generated (if enabled). The TX_STAT bitmap is latched until the
TX_STATUS register is read by the host.
0x1b0
This register implements a mailbox for communication between the host and local processors. LP_MBOX is
written by the host processor and read by the local processor to pass messages in that direction. Writes to this
register can interrupt the local processor while reads can interrupt the host processor.
14-28
31–22
21–16
15–14
31–8
13–8
7–0
7–6
5–0
Bit
31–0
Bit
Bit
—
—
AALx_STAT Register (AALx_STAT)
Local Processor Mailbox Register (LP_MBOX)
Field
Size
Field
Size
24
10
Field
8
Size
6
2
6
2
6
32
Reserved
TX_STAT[7:0]
Reserved
AALx_RSM_OVFL[5:0]
Reserved
AALx_RSM_UNFL[5:0]
Reserved
AALx_SEG_OVFL[5:0]
LP_MBOX[31:0]
Name
Name
Name
Mindspeed Technologies
Set to 0.
Status of Tx port x.
Always read as 0.
A cell was discarded since the ingress FIFO buffer of port x was full.
Always read as 0.
A HFIFORDx edge was detected when the ingress FIFO buffer shadow
counter was empty.
Always read as 0.
A HFIFOWRx edge was detected when the egress FIFO buffer shadow
counter was full.
Local processor mailbox register. Messages flow from host processor to
local processor.
ATM ServiceSAR Plus with xBR Traffic Management
™
Description
Description
Description
28236-DSH-001-B
CN8236