CN8236EBGB Mindspeed Technologies, CN8236EBGB Datasheet - Page 78

• Manufacturer Part Number: CN8236EBGB
• Description: ATM SAR 155Mbps 3.3V ABR/CBR/GFR/UBR/VBR 388-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8236EBGB

• Package: 388BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 155 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V

3.0 Host Interface
3.3 Write-only Control and Status
3-10
3.3.2.4 Status Queue
Interrupt Delay
Status Queue Interrupt Delay has been added in order to reduce the interrupt
processing load on the host. This is valuable in a Network Interface Card
(NIC)-based solution, where the SAR resides in an environment in which the host
is not dedicated to datacom processing. Both a timer hold-off mechanism and an
event counter mechanism are implemented and work in parallel. The timer
hold-off mechanism uses the ALARM1 and CLOCK register resources to
implement an interval timer. Interrupts due to status queue writes, either host or
local, are delayed until the timer expires. The event counter mechanism delays the
assertion of the interrupt due to status queue writes until a fixed number of status
queue writes have occurred. Both mechanisms work in parallel (not in series) if
enabled, so that either mechanism needs to expire before the interrupt propagates
to the output pin. Interrupts due to conditions other than status queue writes are
not delayed.
Timer Hold-off Mechanism
The timer hold-off mechanism is enabled by setting INT_DELAY (EN_TIMER)
to a logic high. The ALARM1 register is set to a value that holds off the interrupt
for a specified period of time. The user initializes the CLOCK register to 0. When
the value in the CLOCK register is greater than the value in the ALARM1
register, status queue interrupts are allowed to propagate to the appropriate
interrupt pins, HINT* or PINT*. The CLOCK register is set to 0 once an interrupt
has propagated to the output pin, thus closing the status queue write interrupt
window. The timer mechanism cannot be used in both the PINT* and HINT*
circuits at the same time. The timer mechanism is configured via the
INT_DELAY (TIMER_LOC) bit.
Event Counter Mechanism
The event counter mechanism is enabled by setting INT_DELAY
(EN_STAT_CNT) to a logic high. An internal counter is implemented that counts
the number of status queue write events. The number of events before opening the
interrupt window is programmable via the INT_DELAY(STAT_CNT) field. The
window is closed for STAT_CNT number of events. When the internal counter
has reached the value of STAT_CNT, the interrupt window is opened, which
allows the interrupt to propagate to the output pin. The counter is reset when the
status registers are read and the interrupt output goes inactive.
Mindspeed Technologies
ATM ServiceSAR Plus with xBR Traffic Management
™
28236-DSH-001-B
CN8236