CN8236EBGB Mindspeed Technologies, CN8236EBGB Datasheet - Page 250

• Manufacturer Part Number: CN8236EBGB
• Description: ATM SAR 155Mbps 3.3V ABR/CBR/GFR/UBR/VBR 388-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8236EBGB

• Package: 388BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 155 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V

8.0 DMA Coprocessor
8.4 Misaligned Transfers
Figure 8-1. LIttle Endian Aligned Transfer
8-2
Length(# of 32 bit words) = 3
PCI Host Address Space
8.4 Misaligned Transfers
The reassembly and segmentation coprocessors handle data internally on word
addresses. The DMA coprocessor must be capable of handling transfers from the
PCI bus without the same constraint, that is, with data that is not aligned on word
boundaries. In addition, the length of the transfer is specified in bytes, not 32-bit
words, even though the data bus widths are all 32 bits.
CN8236 specifies a host address with the Least Significant Bits (LSBs) = 00, it is
implied that the data is byte aligned.
address would map into the PCI host address space for a little endian system.
Selecting between big and little endian systems is done using the ENDIAN [bit
12] in Configuration register 0 [CONFIG0;0x14].
ATM Cell
To facilitate this, byte-switching logic is used within the CN8236. When the
Mindspeed Technologies
0
1
Host Address = 00 from RSM block
2
3
11
3
7
4
10
Bytes
2
6
5
1
5
9
ATM ServiceSAR Plus with xBR Traffic Management
6
0
4
8
7
Figure 8-1
8
0x00
0x04
0x08
™
9
10
Address
11
illustrates how a byte-aligned
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CN8236
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