CN8236EBGB Mindspeed Technologies, CN8236EBGB Datasheet - Page 322

• Manufacturer Part Number: CN8236EBGB
• Description: ATM SAR 155Mbps 3.3V ABR/CBR/GFR/UBR/VBR 388-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8236EBGB

• Package: 388BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 155 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V

14.0 CN8236 Registers
14.2 System Registers
0x14
This register provides all control and configuration bits that are not associated with the reassembly and
segmentation coprocessors. The majority of these configuration bits are set at initialization time and are not
changed dynamically. The assertion of the HRST* system reset pin clears all of the bits in the CONFIG0
register except for MEMCTRL, which is set high.
14-6
20–16
Bit
31
30
29
28
27
26
25
24
23
22
21
15
14
13
12
—
Configuration Register 0 (CONFIG0)
Field
Size
1
1
1
1
1
1
1
1
1
1
1
5
1
1
1
1
LP_ENABLE
GLOBAL_RESET
PCI_MSTR_RESET
PCI_ERR_RESET
Reserved
8223_MODE
PHY2_EN
INT_LBANK
PCI_WR_RD
PCI_READ_MULTI
PCI_ARB
STATMODE[4:0]
FR_RMODE
(BT8222/3)
FR_LOOP
UTOPIA_MODE
ENDIAN
Name
Mindspeed Technologies
When set, this bit causes the PRST* output pin to be high. This can be
used to reset the local processor.
When set, this bit causes reset of the segmentation and reassembly
coprocessors and all latched status.
When set, this bit resets the PCI master logic. Once active, this bit must
stay active for 16 cycles of the HCLK input signal.
When set, resets all PCI error bits in the PCI configuration, including RMA,
RTA, DPR, INTF_DIS, INT_FAIL, and MERROR. This also re-enables PCI
master operation.
Always set to 0.
When set, enables modified microprocessor interface timing to PHY.
Enables the second PHY device memory space in standalone operation.
When set, allows only byte 0 and 1 writes to address space
0x1000–0x10ff and 0x1400–0x14ff. This allows endian neutral access of
the Status Queue Base Table READ_UD field by the host or local
processor.
When this bit is high, the PCI Master Arbitration Scheme is set to write
priority over read. This bit takes precedence over PCI_ARB (bit 21).
When this bit is set, the SAR’s PCI Master implements the PCI Read
Multiple Command. Otherwise, the PCI Master implements the PCI Read
Command.
Selects PCI Master arbitration scheme. When a logic high, enables
round-robin between read and write requests. When a logic low, reads
have priority over writes.
Selects which internal status to output on the STAT[1:0] output pins.
Controls reassembly start of cell processing. When set low, processing
starts after the first two words of a cell are received. When set high, a
complete cell must be in reassembly FIFO buffer before cell is processed.
When set, this bit enables loopback of cells at the ATM physical interface.
Loopback uses SYSCLK.
Selects byte or cell UTOPIA handshake mode.
0 = Octet handshake
1 = Cell handshake
Selects between Little and Big Endian host data structures.
0 = Little Endian
1 = Big Endian
ATM ServiceSAR Plus with xBR Traffic Management
™
Description
28236-DSH-001-B
CN8236