CN8236EBGB Mindspeed Technologies, CN8236EBGB Datasheet - Page 177

• Manufacturer Part Number: CN8236EBGB
• Description: ATM SAR 155Mbps 3.3V ABR/CBR/GFR/UBR/VBR 388-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8236EBGB

• Package: 388BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 155 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V

Table 6-3. Selection of Schedule Table Slot Size by System Requirements
CN8236
ATM ServiceSAR Plus with xBR Traffic Management
28236-DSH-001-B
NOTE(S):
(1)
(2)
Service
CBR
VBR_OFFSET would be set to 0 for this mode of operation.
The bottom four rows of this table describe the slot size formats when USE_SCH_CTRL is not asserted.
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
Number of
VBR/ABR
Priorities
Required
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
and the CBR_TUN bit in the SEG_CTRL register. If the USE_SCH_CTRL bit in
the SEG_CTRL register is not asserted, the user controls the size and format of all
schedule slots through the DBL_SLOT, 3-bit VBR_OFFSET, and CBR_TUN
fields in the SEG_CTRL register. These factors, coupled with the size of the
Schedule table, determine the memory requirements for the Schedule table.
8 Words (256 bits)
8 Words (256 bits)
7 Words (224 bits)
7 Words (224 bits)
6 Words (192 bits)
6 Words (192 bits)
5 Words (160 bits)
5 Words (160 bits)
4 Words (128 bits)
4 Words (128 bits)
3 Words (96 bits)
3 Words (96 bits)
2 Words (64 bits)
2 Words (64 bits)
1 Word (32 bits)
1 Word (32 bits)
Schedule Slot
Size
Mindspeed Technologies
CBR_TUN
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
(DBL_SLOT = 1)
(DBL_SLOT = 1)
(DBL_SLOT = 0)
(DBL_SLOT = 0)
SLOT_DEPTH
™
6.2 xBR Cell Scheduler Functional Description
111
111
110
110
101
101
100
100
011
011
010
010
001
001
000
000
(2)
(2)
(2)
(2)
6.0 Traffic Management
VBR_OFFSET + 0 or 1
VBR_OFFSET + 0–13
VBR_OFFSET + 1–13
VBR_OFFSET + 0–11
VBR_OFFSET + 1–11
Available VBR/ABR
VBR_OFFSET + 0–9
VBR_OFFSET + 1–9
VBR_OFFSET + 0–7
VBR_OFFSET + 1–7
VBR_OFFSET + 0–5
VBR_OFFSET + 1–5
VBR_OFFSET + 0–3
VBR_OFFSET + 1–3
VBR_OFFSET + 1
Priority Levels
0–15
1–15
(1)
(1)
6-9