CN8236EBGB Mindspeed Technologies, CN8236EBGB Datasheet - Page 306
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CN8236EBGB
Manufacturer Part Number
CN8236EBGB
Description
ATM SAR 155Mbps 3.3V ABR/CBR/GFR/UBR/VBR 388-Pin BGA
Manufacturer
Mindspeed Technologies
Datasheet
1.CN8236EBGB.pdf
(443 pages)
Specifications of CN8236EBGB
Package
388BGA
Traffic Class
ABR|CBR|GFR|UBR|VBR
Utopia Type
Level 1|Level 2
Host Interface
PCI
Maximum Data Rate
155 Mbps
Typical Operating Supply Voltage
3.3 V
Minimum Operating Supply Voltage
3 V
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12.0 ATM UTOPIA Interface
12.7 Slave Level 1 UTOPIA Mode
Figure 12-6. Receive Timing in Slave UTOPIA Level 1 Mode
12-16
RXD/RXPAR
NOTE(S):
(1)
(2)
(3)
RXCLAV
RxSOC
RXCLK
RxClav goes inactive when there is room in the receive FIFO buffer for a complete cell.
RxClav goes active when there is no longer room in the receive FIFO buffer for another complete cell.
RxEN* need not be inactive when RxClav is active.
RXEN*
(1)
H1
12.7 Slave Level 1 UTOPIA Mode
The slave UTOPIA mode is similar to the UTOPIA mode, except the direction of
the enable signals and FIFO buffer flags are reversed. This allows a switch fabric
or backplane to directly control the physical port. The transmit and receive enable
signals are generated by the physical layer instead of the CN8236. The TxFull*
signal is changed to the TxEmpty* signal and is an output of the CN8236. The
RxEmpty* signal is changed to the RxFull* signal, and is also an output of the
CN8236. This mode supports only a cell-level handshake protocol.
edge of RXCLK when RxEN* is active (see
computed over the RxData[15:0] lines is compared to the RxPar input. If there is
a parity error, the FR_PAR_ERR bit is set in the HOST_ISTAT0/LP_ISTAT0
registers. Data is discarded upon a parity error if the RSM_PHALT bit in the
RSM_CTRL register is set to a logic high. If so, the reassembly coprocessor halts
upon a parity error. The RxSOC signals to the CN8236 the start of cell. The
RxClav output is the receive FIFO buffer full signal. When it is active, the
CN8236 cannot accept another cell. The CN8236 sets RxClav inactive when it
has room in the receive FIFO buffer for another cell. The physical device sets
RxEN* to a logic low if it can transfer an octet. The FR_RMODE bit in the
CONFIG0 register should be set to a logic low in this mode.
H2
Received data is latched from the RxData[15:0] and RxPar lines on the rising
X
Mindspeed Technologies
H3
***
P44
ATM ServiceSAR Plus with xBR Traffic Management
P45
P46
™
Figure
(2)
P47
12-6). The odd parity
P48
X
(3)
28236-DSH-001-B
X
H1
CN8236
8236_075
H2
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