CN8236EBGB Mindspeed Technologies, CN8236EBGB Datasheet - Page 77

• Manufacturer Part Number: CN8236EBGB
• Description: ATM SAR 155Mbps 3.3V ABR/CBR/GFR/UBR/VBR 388-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8236EBGB

• Package: 388BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 155 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V

CN8236
ATM ServiceSAR Plus with xBR Traffic Management
Figure 3-5. Write-only Status Queue
28236-DSH-001-B
READ++
3.3.2.3 Overflow
Conditions
0 0 0 0
UPDATE++
1
1 1 1 1 1 1 1 1
BASE_PNTR
(Base table)
services an entry, it increments a counter (UPDATE++). When this counter
reaches a host-specified threshold (INTERVAL), the host informs the SAR of its
current queue position by writing READ_UD in the queue’s base table register.
An overflow condition occurs when the SAR attempts to write a status queue
entry, but the status queue entry is unavailable. This condition can happen for
both the segmentation and reassembly status queues.
describe the handling of this event. In either case, the result is severe and
therefore undesirable. The host control service rate of the status queue should
match or exceed the status queue reporting rate of the CN8236.
pointer to the READ_UD pointer, that is, the last known host READ position. If
WRITE points to the entry immediately before the READ_UD
(WRITE = READ_UD -1), the SAR detects the imminent overflow condition.
(OVFL) in the exhausted status queue. Since it cannot report status, the CN8236
segmentation and reassembly processing is temporarily halted for VCCs assigned
to the overflowed status queue only. All other processes and queues remain
operational.
The host also maintains a pointer (READ) into the status queue. Each time it
The CN8236 detects an overflow condition by comparing its current WRITE
To inform the host of the event, the SAR sets the overflow indication bit
1
1
1 1 1 1 1 1 1 1 1
INTERVAL
UPDATE=
Mindspeed Technologies
N
Y
0 0 0 0 0 0 0 0
READ_UD_PNTR=
Update SAR
UPDATE=0
READ
VLD
bit
Boundary
PCI Bus
™
READ_UD - 1
READ_UD_PNTR
WRITE =
3.3 Write-only Control and Status
Chapter 4.0
N
Y
3.0 Host Interface
and
Overflow
(Base Table)
(Base Table)
Chapter 5.0
READ_UD
Signal
WRITE++
8236_102
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