CN8236EBGB Mindspeed Technologies, CN8236EBGB Datasheet - Page 365

• Manufacturer Part Number: CN8236EBGB
• Description: ATM SAR 155Mbps 3.3V ABR/CBR/GFR/UBR/VBR 388-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8236EBGB

• Package: 388BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 155 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V

CN8236
ATM ServiceSAR Plus with xBR Traffic Management
15.2.1 Scheduler Control Registers
28236-DSH-001-B
Table 15-4. Table of Values for Scheduler Control Register Initialization
SCH_PRI
(Schedule Priority
Register)
SCH_SIZE
(Schedule Size Register)
SCH_ABR_MAX
(Schedule Maximum ABR
Register)
PCR_QUE_INT01
(PCR Queue Interval 0 and
1 Register)
PCR_QUE_INT_23
(PCR Queue Interval 2 and
3 Register)
SCH_ABR_CON
(Schedule ABR Constant
Register)
SCH_ABRBASE
(ABR Decision Table
Lookup Base Reg)
SCH_CNG
(ABR Congestion
Register)
Register
TUN_ENA7-0
GFC7-0
QPCR_ENA7-0
TBL_SIZE
SLOT_PER
VCC_MAX
QPCR_INT0
QPCR_INT1
QPCR_INT2
QPCR_INT3
ABR_TRM
ABR_ADTF
OOR_ENA
OOR_INT
SCH_ABRB
FBQ_CNG
15.2 Scheduler Initialization
Before segmentation is enabled, the host must allocate and initialize all of the
Scheduler control registers.
Field
Mindspeed Technologies
Initialized Value
0x1C9D
0x16C
0x23C
0xB2E
0x1D1
0x5B
0x63
0x04
0x80
0x0
0x0
0x0
0x0
0
0
1
Table 15-4
lists the initialized values for each field.
No tunnels enabled.
No GFC priorities enabled.
Enable PCR limits on queue 2.
Schedule table consists of 128 entries.
Schedule slot period is 91 SYSCLK periods.
Enable 50 channels of ABR processing.
Not used since only one global PCR queue
enabled.
Not used since only one global PCR queue
enabled.
Not used since only one global PCR queue
enabled.
PCR interval = 364 schedule slots.
Set TRM to TM 4.1 default of 100 ms.
Set ADTF to TM 4.1 default of 0.5 second.
Enable out-of-rate ABR RM cells.
Produces an out-of-rate interval of one cell
per second.
ABR table starts at 0xE880 in SAR-shared
memory.
No congestion experienced.
™
15.0 SAR Initialization—Example Tables
15.2 Scheduler Initialization
Notes
15-5