CN8236EBGB Mindspeed Technologies, CN8236EBGB Datasheet - Page 266

• Manufacturer Part Number: CN8236EBGB
• Description: ATM SAR 155Mbps 3.3V ABR/CBR/GFR/UBR/VBR 388-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8236EBGB

• Package: 388BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 155 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V

10.0 Local Processor Interface
10.3 Bus Cycle Descriptions
10.3.3 Double Read Burst With Processor Wait States
Figure 10-4. Local Processor Double Read with Wait States Inserted
10-8
LADDR[18:2]
LDATA[31:0]
PADDR[1:0]
LADDR[1:0]
PBSEL[1:0]
MWE*[3:0]
MCS*[3:0]
PBLAST*
SYSCLK
PBE[3:0]
PDAEN*
PWAIT*
PRDY*
D[31:0]
A[20:4]
PWNR
DT/R*
MOE*
PCS*
PAS*
1.
Address
Cycle
ta
10
00
1
In
additional time for the reads to occur. At the rising edge of SYSCLK on cycle 4
and cycle 6, the combination of PWAIT* low and PRDY* low extends the read by
one more cycle. The local processor word select inputs (PADDR[1:0]) are latched
at cycle 1. The CN8236 word select address lines, LADDR[1:0], are incremented
automatically at the beginning of cycle 6.
2.
Figure
Arbitration
Cycle
tarb
Mindspeed Technologies
10-4, the processor inserts wait states on cycle 4 and cycle 6 to allow
2
3.
Bus
Recovery
Cycle
tbr
3
4.
tw
Wait
Cycle
A0
A0
ATM ServiceSAR Plus with xBR Traffic Management
4
5.
Data
Cycle
td
1101
™
D0
D0
00
5
6. Wait
tw
Cycle
6
7.
Data
Cycle
td
D1
D1
01
28236-DSH-001-B
7
CN8236
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