MT90840AP Zarlink, MT90840AP Datasheet - Page 12

• Manufacturer Part Number: MT90840AP
• Description: Switch Fabric 512 x 2430/512 x 512/2.373K x 2.373K 5V 84-Pin PLCC Tube
• Manufacturer: Zarlink

Specifications of MT90840AP

• Package: 84PLCC
• Number Of Ports: 16
• Fabric Size: 512 x 2430|512 x 512|2.373K x 2.373K
• Switch Core: Non-Blocking
• Port Speed: 8.192|4.096|2.048 Mbps
• Operating Supply Voltage: 5 V

Serial Data Port
The serial port consists of 16 bidirectional serial data lines (STo0-7, STi0-7), two reference input clock pins
(C4/8R1, C4/8R2), one serial clock output (SPCKo) and a bidirectional frame synchronization signal (F0i/o). The
STi pins are the default inputs, but the user can program the direction of the pins on a per-channel basis in the Rx
Path Connection Memory.
The serial port modes are controlled by the DR bits and the FDC bit in the IMS register, and are:
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Figure 3 shows the different data rate configurations for the MT90840 serial port.
In addition the user can specify the placement and polarity of the output frame pulse F0o as ST-BUS or GCI
compatible, using the SPFP bit in the GPM register. In TM1, the MT90840 automatically detects ST-BUS or GCI
serial bus modes, based on the polarity of F0i. The user can also specify which of the two input clock pins - C48R1
or C48R2 - to use as the serial port clock source, using the C4/8R bit in the TIM register.
The user can define the direction of each time slot of the serial port. This per-channel direction control feature is
controlled by the DC bit in the Rx Path Connection Memory High. This is ideal for applications in Computer
Telephony Integration (CTI) where per-channel direction control is required within telephony servers.
2.048 Mbps Balanced Mode
The 2.048 Mbps Balanced mode has 8 inputs and 8 outputs active during each serial-byte-period or “time slot”. At
2.048 Mbps, each STi/o pin has 32 8-bit channels per 125 µsec frame, with each individual channel at 64 kbps.
(1/125µsec X 8 bits = 64 kbps, 32 x 64 kbps = 2.048 Mbps). This mode supports 256 serial input channels and 256
serial output channels. This mode is “balanced” in that there are always 8 inputs and 8 outputs during a time slot. If
a specific time slot in an output stream (e.g. STo0-channel7) is programmed in the Rx Path Connection Memory as
an input, the corresponding time slot on the equivalent input stream (i.e. STi0-channel7) is automatically an output.
The serial clock for this mode is 4.096 MHz.
2.048 Mbps Add/Drop Mode
The 2.048 Mbps Add/Drop mode (FDC bit high) has 16 bidirectional streams active during each time slot. This
mode allows up to 512 input channels, or up to 512 output channels, or any mix of channels totalling 512 channels.
Per-channel direction control in the Rx Connection Memory specifies the direction of all 512 serial channels from
STo0-channel0 up to STi7-channel31.
4.096 Mbps Mode
The 4.096 Mbps mode has 8 inputs and 8 outputs active during each time slot. At 4.096 Mbps each STi/o pin has
64 channels of 64 kbps. This mode supports 512 serial input channels and 512 serial output channels. The serial
clock is 4.096 MHz. Per-channel direction control in this mode is the same as the 2.048 Mbps balanced mode.
8.192 Mbps Mode
The 8.192 Mbps mode has 4 inputs and 4 outputs active during each serial byte period. At 8.192 Mbps, each STi/o
pin has 128 channels. This mode supports 512 serial input channels and 512 serial output channels. The serial
clock for this mode is 8.192 MHz. Per-channel direction control in this mode is the same as the 2.048 Mbps
balanced mode.
2.048 Mbps Balanced: 8 inputs and 8 outputs per serial time slot (FDC = 0),
2.048 Mbps Add/Drop: 16 serial I/O individually programmed per time slot (FDC = 1),
4.096 Mbps: 8 inputs and 8 outputs per time slot,
8.192 Mbps: 4 inputs and 4 outputs per time slot.
Zarlink Semiconductor Inc.
MT90840
12
Data Sheet