MT90840AP Zarlink, MT90840AP Datasheet - Page 36

• Manufacturer Part Number: MT90840AP
• Description: Switch Fabric 512 x 2430/512 x 512/2.373K x 2.373K 5V 84-Pin PLCC Tube
• Manufacturer: Zarlink

Specifications of MT90840AP

• Package: 84PLCC
• Number Of Ports: 16
• Fabric Size: 512 x 2430|512 x 512|2.373K x 2.373K
• Switch Core: Non-Blocking
• Port Speed: 8.192|4.096|2.048 Mbps
• Operating Supply Voltage: 5 V

Timing Mode Register (TIM) - READ/WRITE
TM1-0
C4/8R
TCP
INTCLK Internal 4.096 MHz Clock Divider. For use in TM2, in 19.44 or 16.384 MHz parallel-port applications. This bit controls the
SFDI
PFDI
Note: Bit 7 must be set to 0 by the CPU.
Timing Mode control bits. Define the four different timing modes described in the Timing and Switching Control section.
0 0
0 1
1 0
1 1
C4/8R Input Reference Select. If set high, this bit enables the 4.096 or 8.192 MHz serial port reference clock to be taken from
Parallel Port Transmit Clock Polarity. To allow the MT90840 parallel port transmit clock to comply with different 155 Mbps
Serial Frame Pulse Direction Control. Normally LOW, unless it is necessary to operate multiple parallel MT90840 devices in
Parallel Frame Pulse Direction Control. Normally LOW, unless it is necessary to operate multiple parallel MT90840 devices in
input pin C4/8R1. If LOW, the reference is taken from input pin C4/8R2 (default).
framer backplanes, TCP controls which edge of the clock is used to transmit data at the parallel port. (The clock is PCKT in
TM1 or PCKR in TM2, 3, & 4). The TCP bit allows the rising (TCP=LOW) or the falling (TCP=HIGH) edges of the transmit
clock to be selected.
operation of the internal clock divider driven by PCKR. When INTCLK is set HIGH the internal 4.096 MHz clock (and the
SPCKo output) are generated by dividing down the PCKR clock. When INTCLK is set LOW, the C4/8R bit controls the source
for the serial clock reference. In TM3 and TM4 the MT90840 automatically sets itself in the internal divider mode and the state
of INTCLK has no effect. In TM1 this bit is must be set LOW.
Timing Mode 2. When set HIGH, the F0 line becomes an input and this MT90840 is synchronized to the timing of another
MT90840 generating the F0o, and using the same 4.096 or 8.192 MHz reference input. One MT90840 in TM2 with SFDI LOW
can control several MT80940s with SFDI HIGH. When SFDI is set HIGH, INTCLK is ignored, and SPFP in the GPM register
must be set to the expected F0i polarity.
Timing Mode 1. When set HIGH, the PPFT pin becomes an input and this MT90840 is synchronized to the timing of another
MT90840 generating the PPFTo. One MT90840 in TM1 with PFDI LOW can control several MT80940s with PFDI HIGH.
When PFDI is HIGH, PPFP in the GPM register must be set to the expected PPFTi polarity.
0
7
Timing Mode 1
Timing Mode 2
Timing Mode 3
Timing Mode 4
TM1
6
TM0
5
C4/8R
4
Zarlink Semiconductor Inc.
TCP
3
MT90840
INTCLK SFDI
36
2
1
PFDI
0
Data Sheet