MT90840AP Zarlink, MT90840AP Datasheet - Page 9

• Manufacturer Part Number: MT90840AP
• Description: Switch Fabric 512 x 2430/512 x 512/2.373K x 2.373K 5V 84-Pin PLCC Tube
• Manufacturer: Zarlink

Specifications of MT90840AP

• Package: 84PLCC
• Number Of Ports: 16
• Fabric Size: 512 x 2430|512 x 512|2.373K x 2.373K
• Switch Core: Non-Blocking
• Port Speed: 8.192|4.096|2.048 Mbps
• Operating Supply Voltage: 5 V

Device Operation
Time Slot Interchange Operation (Switching)
The MT90840 provides access and time slot interchange (switching) functions between the serial and parallel TDM
data ports. Switching is provided on three paths: transmit (serial input to parallel output), receive (parallel input to
serial output) and bypass/parallel-switching (parallel input to parallel output). Switching functions between serial
data streams are not provided.
The MT90840 guarantees wideband or hyper-channel data integrity through the switch by using constant delay
switching. This is done by storing a full frame (125 µsec) of data at the input rate and then, under control of the
Connection Memory for that path, reading the frame at the output data rate (frame integrity). Therefore the Transmit
Path and the Receive Path each have separate Data and Connection Memories.
Switching in a given data path is controlled by programming the Connection Memory for that path. Each output time
slot has a control-address in the path’s Connection Memory. Each input time slot has an address-value in the path’s
Data Memory. A given output time slot is controlled by programming the Connection Memory control-address with
the address-value of the source input time slot. At the same control-address the output time slot is enabled or tri-
stated and other per-channel functions set up. Thus each output time slot is individually controlled, and any given
input time slot might be copied to one, several, or none of the output time slots.
C4/8R1&2
(4 MHz)
Serial I/O
2 Mbps
Serial I/O
4 Mbps
C4/8R1&2
(8 MHz)
Serial I/O
8 Mbps
Ch. 31 Bit 1
Ch. 63 Bit 2
ch.127
Figure 3 - Serial Port Interface Functional Timing
Ch. 63 Bit 1
b3
ch.127
b2
Ch. 31 Bit 0
Frame Boundary Established by F0
ch.127
Zarlink Semiconductor Inc.
b1
Ch. 63 Bit 0
MT90840
ch.127
b0
9
ch. 0
b7
Ch. 0 Bit 7
ch. 0
b6
Ch. 0 Bit 7
ch. 0
b5
Ch. 0 Bit 6
ch. 0
b4
Ch. 0 Bit 5
Ch. 0 Bit 6
Data Sheet