MT90840AP Zarlink, MT90840AP Datasheet - Page 20

• Manufacturer Part Number: MT90840AP
• Description: Switch Fabric 512 x 2430/512 x 512/2.373K x 2.373K 5V 84-Pin PLCC Tube
• Manufacturer: Zarlink

Specifications of MT90840AP

• Package: 84PLCC
• Number Of Ports: 16
• Fabric Size: 512 x 2430|512 x 512|2.373K x 2.373K
• Switch Core: Non-Blocking
• Port Speed: 8.192|4.096|2.048 Mbps
• Operating Supply Voltage: 5 V

Enable, and Message Mode. On the serial port the per-channel features are Output Enable, Message Mode and
Direction Control. These functions are generally available in all of the data rates and timing/switching modes.
Per-channel Bypass on the Parallel Port
This feature, when enabled, causes the specific individual parallel output channel at PDo to transmit the data
received at the same number input channel at PDi. This can be used to perform a bypass (on a ring) or a loopback
(in a star). This feature is only provided in Timing Modes 1 and 2. In TM2 the data-delay from PDi to PDo is fixed (as
is the delay between PPFRi and PPFT). In TM1 the data-delay is elastic (and dependent on the timing of PPFRi
and F0i).
The per-channel bypass feature is controlled by the PPBY bits of the TPCM High as explained in the register
section. If the PPBY bit is HIGH at a specific TPCM address, the corresponding parallel output will transmit the data
received in the corresponding input channel. When the PPBY bit is LOW, the corresponding output channel can be
used for message-mode data, or for switched-data from the serial port. A bypass input channel is still copied to the
Receive Path Data Memory, and may also be switched to the serial port, or read by the CPU from the Receive Path
Data Memory.
The MT90840 per-channel output-enable and message-mode bits have higher priority than the PPBY bit.
TM1, TM2,
or TM3 S/P
TM1P/S
TM2 P/S
TM3 P/S
TM1 P/P
(Bypass)
TM2 P/P
(Bypass)
TM4 P/P
(Switching)
TM1 S/P +
TM2 P/S
TM2 S/P +
TM1 P/S
Mode
All
All
All
All
All
19.44 Mbyte/s
16.384 Mbyte/s
6.480 Mbyte/s
19.44 & 16.384
Mbyte/s
All
All
Data Rates
Dmin = 7.7
Note 1
Dmin = ELDmin
= 4.4
Note 2
Dmin = 4.3
Note 1
Dmin = 1 frame -
7.7
= 117.3
Dmin = 12
frame
= 137
Note 2
Note 3
Dmin = {3.5 or 4}
PCKR cycles
(TCP bit = 1 or 0)
Dmin = 12
frame
= 137
Dmin = 12
frame
= 137.4
Minimum Delay
µ
sec
µ
µ
µ
sec
sec
sec
µ
µ
sec
sec
µ
µ
µ
µ
µ
Zarlink Semiconductor Inc.
sec + 1
sec + 1
sec + 1
sec
sec
MT90840
20
D = Dmin + 1 frame + Po - Si = 132.7
Min. 7.7
D = 1 frame + ELD + So - Pi = 125
Min. 4.4
D = Dmin + 1 frame + So - Pi = 129.3
Min. 4.3
T = Dmin + 1 frame + So - Pi = 242.3
Min. 117
D = 7.7
Min.137
D = {235 or 235.5} PCKR cycles = 12
D = {199 or 199.5} PCKR cycles = 12
D = {80 or 80.5} PCKR cycles = 12
D = Dmin + 1 frame + Po - Pi
Min. < 0.3
D = 12
= 262
D = 12
= 262
µ
µ
µ
µ
sec + Transmission + So - Si
sec + Transmission + ELD + So - Si
µ
s + 2 frames + Transmission + So - Si
sec + 2 frames + Transmission + ELD + So - Si
µ
µ
µ
µ
sec + 1 frame + ELD
µ
sec, Avg. 133
sec, Max. 379
sec, Avg. 129
sec, Max. 262
sec, Avg. 242
µ
sec, Avg. 125
Total Throughput Delay
µ
µ
µ
µ
µ
sec, Max. 258
sec, Max. 254
sec
sec, Max. 367
sec
µ
sec, Max. 250
µ
µ
sec + ELD + So - Pi
sec
µ
µ
µ
µ
µ
sec + So - Pi
sec + Po - Si
sec + So - Pi
µ
µ
sec
sec
µ
sec
sec
sec
µ
sec
Data Sheet