MT90840AP Zarlink, MT90840AP Datasheet - Page 31

• Manufacturer Part Number: MT90840AP
• Description: Switch Fabric 512 x 2430/512 x 512/2.373K x 2.373K 5V 84-Pin PLCC Tube
• Manufacturer: Zarlink

Specifications of MT90840AP

• Package: 84PLCC
• Number Of Ports: 16
• Fabric Size: 512 x 2430|512 x 512|2.373K x 2.373K
• Switch Core: Non-Blocking
• Port Speed: 8.192|4.096|2.048 Mbps
• Operating Supply Voltage: 5 V

The interrupt source bits can also be monitored during block-programming. If PPCE, or RXPAA (in TM2), or TXPAA
(in TM1), is asserted during block-programming, a framing error has occurred and the block-programming should
be repeated.
Timing Mode Initialization
On system power-up, the CPU should program the MT90840 IMS, GPM, and TIM registers to establish the data
rates, the Timing Mode (1,2,3,4), and the framing polarity of the device. The MT90840 will then adjust its internal
rate conversion and time interchange circuits to accommodate the different rates set at both data ports.
To perform the rate conversions between the serial and the parallel ports, the MT90840 provides a phase alignment
circuit, monitored by the RXPAA and TXPAA interrupt bits. In TM1 and in TM2 with external clocks (INTCLK=0) the
phase alignment circuit works automatically to maintain the relative phase of the serial and parallel ports. The DIN
bit in the GPM register works with this circuit by reducing the window, forcing the phase alignment circuit to center
the relative phases.
After the parallel and serial port reference clocks (PCKT/PCKR and C4/8R1/C4/8R2) are stable, the DIN bit in the
GPM Register can be set HIGH. The DIN bit will auto-reset itself after 8 frames, returning to LOW. (It can also be
written LOW by the CPU.) The DIN bit procedure is especially useful in TM2. In TM1 the DIN bit also centers the
phase relation, but the movement of the transmit parallel port timing during the 8 frames that DIN is asserted may
cause data or framing errors in connected devices. The RPCM and TPCM should not be written to by the CPU
while DIN is asserted.
JTAG Support
The MT90840 boundary-scan circuitry functions in accordance with IEEE Std 1149.1a (often referred to as JTAG
boundary-scan). The standard specifies a design-for-testability technique called Boundary-Scan Test (BST). A
boundary-scan IC has a shift-register stage or ‘Boundary-Scan Cell’ (BSC) in between the core logic and the I/O
buffers adjacent to each I/O pin. The boundary-scan cellscan control and observe what happens at each I/O pin of
the IC. The operation of the boundary-scan circuitry is controlled by a Test Access Port (TAP) Controller.
Test Access Port (TAP)
The Test Access Port (TAP) has five signals and provides access to the test logic defined by the JTAG standard.
The TAP has the following connections:
•
TCK provides the clock for the test logic. TCK is independent of the MT90840 functional clocks; this permits serial
shifting of test data along the Boundary-Scan chain concurrent with the normal operation of the MT90840.
Test Clock Input (TCK)
BSC
Figure 15 - A Typical Boundary-Scan IC
BOUNDARY -SCAN CELL(BSC)
BSC
BSC
BSC
CORE LOGIC
Zarlink Semiconductor Inc.
BSC
MT90840
BSC
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BSC
BSC
T
A
P
C
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N
T
R
O
L
L
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TEST DATA IN (TDI)
TEST CLOCK (TCK)
TEST DATA OUT (TDO)
TEST MODE
SELECT (TMS)
Data Sheet